Patents by Inventor Feng Pan

Feng Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220385267
    Abstract: A surface acoustic wave (SAW) device having a high electromechanical coupling coefficient based on double-layer electrodes and a preparation method thereof. A structure of the SAW device includes a Cu electrode, a piezoelectric film and an Al electrode on a substrate in sequence. A signal terminal of the Cu electrode is opposite to a ground terminal of the Al electrode. A ground terminal of the Cu electrode is opposite to a signal terminal of the Al electrode. Since Sezawa wave mode that is adopted is formed by coupling film thickness vibration and transverse vibration, a longitudinal electric field (in a direction of thickness of a film) and a transverse electric field (in a propagation direction of SAW) are excited through the double-layer electrodes so that the electromechanical coupling coefficient of the SAW device is improved by changing a coupling pattern between the electric fields and the piezoelectric film.
    Type: Application
    Filed: July 14, 2020
    Publication date: December 1, 2022
    Inventors: Feng PAN, Rongxuan SU, Fei ZENG, Junyao SHEN, Sulei FU
  • Publication number: 20220375790
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 24, 2022
    Inventors: Yu-Jen Chang, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Publication number: 20220375923
    Abstract: An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 24, 2022
    Inventors: Guido Wouter Willem Quax, Dongyong Zhu, Feng Cong, Tingting Pan
  • Publication number: 20220351043
    Abstract: The present disclosure discloses an adaptive high-precision compression method and system based on a convolutional neural network model, and belongs to the fields of artificial intelligence, computer vision, and image processing. According to the method of the present disclosure, coarse-grained pruning is performed on a neural network model by using a differential evolution algorithm first, and the coarse-grained space is quickly searched through an entropy importance criterion and an objective function with good guidance to obtain a near-optimal neural network structure. Then fine-grained search space is built on the basis of an optimal individual obtained from the coarse-grained search, and fine-grained pruning is performed on the neural network model by a differential evolution algorithm to obtain a network model with an optimal structure. Finally, the performance of the optimal model is restored by using a multi-teacher multi-step knowledge distillation network to reach the precision of an original model.
    Type: Application
    Filed: September 27, 2021
    Publication date: November 3, 2022
    Applicants: Chongqing University, University of Electronic Science and Technology of China, Dibi (Chongqing) Intelligent Technology Research Institute Co., Ltd., Star Institute of Intelligent Systems
    Inventors: Yongduan Song, Feng Yang, Rui Li, Shengtao Pan, Siyu Li, Yiwen Zhang, Jian Zhang, Zhengtao Yu, Shichun Wang
  • Patent number: 11490127
    Abstract: Methods and apparatus provide cloud-based video encoding that generates encoded video data by one or more encoders in a cloud platform for a plurality of cloud encoding sessions. The methods and apparatus generate operational improvement tradeoff data in response to operational encoding metrics associated with the one or more encoders and change operational characteristics of the one or more encoders for at least one of the cloud encoding sessions based on the operational improvement tradeoff data.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: November 1, 2022
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Wei Gao, Ihab Amer, Feng Pan, Mingkai Shao, Crystal Sau, Dong Liu, Gabor Sines, Yang Liu
  • Publication number: 20220344497
    Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 27, 2022
    Inventors: Chen-Wei PAN, Jen-Chih HSUEH, Li-Feng CHU, Chih-Teng LIAO
  • Patent number: 11482532
    Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: October 25, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
  • Patent number: 11474548
    Abstract: Embodiments relate to digital low-dropout (DLDO) with fast feedback and optimized frequency response. Certain embodiments may relate more particularly to ferroelectric memory circuit configurations. For example, a low dropout regulator may include a first circuit path configured to regulate an input voltage to an output voltage at a load, wherein the first path comprises a first transistor. The apparatus may also include a second circuit path configured to feed back an error signal based on the input voltage and the output voltage, wherein the second circuit path comprises an error amplifier.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: October 18, 2022
    Assignee: WUXI PETABYTE TECHNOLOGIES CO, LTD.
    Inventor: Feng Pan
  • Publication number: 20220327308
    Abstract: The present disclosure relates to a method for recognizing facial expressions based on adversarial elimination. First, a facial expression recognition network is built based on a deep convolutional neural network. On a natural facial expression data set, the facial expression recognition network is trained through a loss function to make facial expression features easier to distinguish. Then some key features of input images are actively eliminated by using an improved confrontation elimination method to generate a new data set to train new networks with different weight distributions and feature extraction capabilities, forcing the network to perform expression classification discrimination based on more features, which reduces the influence of interference factors such as occlusion on the network recognition accuracy rate, and improving the robustness of the facial expression recognition network.
    Type: Application
    Filed: September 27, 2021
    Publication date: October 13, 2022
    Applicants: Chongqing University, University of Electronic Science and Technology of China, Dibi (Chongqing) Intelligent Technology Research Institute Co., Ltd., Star Institute of Intelligent Systems
    Inventors: Yongduan Song, Feng Yang, Rui Li, Yiwen Zhang, Haoyuan Zhong, Jian Zhang, Shengtao Pan, Siyu Li, Zhengtao Yu
  • Publication number: 20220325380
    Abstract: A tungsten-base alloy material and a preparation method therefor. The preparation method comprises: 1) evenly grinding composite powder containing tungsten and zirconium oxide, and then performing annealing treatment at 700-1000° C. to obtain powder A; and 2) grinding and then compression moulding the powder A, and then performing liquid-phase sintering to obtain a tungsten-base alloy blank so as to obtain the tungsten-base alloy material.
    Type: Application
    Filed: August 12, 2020
    Publication date: October 13, 2022
    Applicant: HENAN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Shizhong WEI, Liujie XU, Fangnao XIAO, Kunming PAN, Yucheng ZHOU, Xiuqing LI, Jiwen LI, Xiran WANG, Xiaodong WANG, Cheng ZHANG, Chong CHEN, Feng MAO, Mei XIONG, Guoshang ZHANG, Dongliang JIN
  • Patent number: 11459279
    Abstract: A supported catalyst for preparing light olefin using direct conversion of syngas is a composite catalyst and formed by compounding component I and component II in a mechanical mixing mode. The active ingredient of component I is a metal oxide; and the component II is a supported zeolite. A carrier is one or more than one of hierarchical pores Al2O3, SiO2, TiO2, ZrO2, CeO2, MgO and Ga2O3; the zeolite is one or more than one of CHA and AEI structures; and the load of the zeolite is 4%-45% wt. A weight ratio of the active ingredients in the component I to the component II is 0.1-20. The reaction process has an extremely high light olefin selectivity; the sum of the selectivity of the light olefin comprising ethylene, propylene and butylene can reach 50-90%, while the selectivity of a methane side product is less than 7%.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 4, 2022
    Assignee: DALIAN INSTITUTE OF CHEMICAL PHYSICS, CAS
    Inventors: Xiulian Pan, Feng Jiao, Xinhe Bao, Gen Li
  • Patent number: 11442687
    Abstract: An audio transmission device coupled to an electronic device and including a detection circuit, a vendor-defined class circuit, and an audio class circuit is provided. The detection circuit detects an external sound to generate an input voice. The vendor-defined class circuit provides a first voice signal to the electronic device according to the input voice. An audio processing application program of the electronic device processes the first voice signal to generate a processed voice to the vendor-defined class circuit. The audio class circuit receives the processed voice from the vendor-defined class circuit, uses the processed voice as a second voice signal, and provides the second voice signal to the media manager of the electronic device.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: September 13, 2022
    Assignee: VIA LABS, INC.
    Inventors: Chih-Hsien Lin, Chin-Sung Hsu, Li-Feng Pan
  • Publication number: 20220285241
    Abstract: A method of forming a semiconductor package includes the following steps. A redistribution layer structure is formed over a first die and a dummy die, wherein the redistribution layer structure is directly electrically connected to the first die. An insulating layer is formed, wherein the insulating layer is disposed opposite to the redistribution layer structure with respect to the first die. At least one thermal through via is formed in the insulating layer.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Ching-Feng Yang, Hsin-Yu Pan, Kai-Chiang Wu, Yi-Che Chiang
  • Publication number: 20220281640
    Abstract: The disclosure provides an adjustable device including plates and at least two adjustable modules connect with two adjacent of the plates. The adjustable module can stretch or shrink to change a distance between plates. The disclosure also provides an adjustable storage box including an upper cover and a lower cover. A storage space is formed by the upper cover and the lower cover and for the accommodating of the adjustable device. When the upper cover moves upward relative to the lower cover, the adjustable modules changes from a compression state to a stretch state and increase a distance between plates. Whereby, it is easy to pick and place object when a distance of two adjacent plates increases. The overall volume of the adjustable device is reduced when a distance of two adjacent plates decrease, thereby saving the working space.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventor: SHIH FENG PAN
  • Patent number: 11420911
    Abstract: A catalyst containing LF-type B acid preparing ethylene using direct conversion of syngas is a composite catalyst and formed by compounding component A and component B in a mechanical mixing mode. The active ingredient of the component A is a metal oxide; the component B is a zeolite of MOR topology; and a weight ratio of the active ingredients in the component A to the component B is 0.1-20. The reaction process has an extremely high product yield and selectivity, with the selectivity for light olefin reaching 80-90%, wherein ethylene has high space time yield and can reach selectivity of 75-80%. Meanwhile, the selectivity for a methane side product is extremely low (<15%).
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: August 23, 2022
    Assignee: DALIAN INSTITUTE OF CHEMICAL PHYSICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Xiulian Pan, Feng Jiao, Xinhe Bao, Yuxiang Chen
  • Patent number: 11416994
    Abstract: Embodiments of the disclosure provide systems and methods for biomedical image analysis. A method may include receiving a plurality of unannotated biomedical images, including a first image and a second image. The method may also include determining that the first image is in a first view and the second image is in a second view. The method may further include assigning the first image to a first processing path for the first orientation. The method may additionally include assigning the second image to a second processing path for the second view. The method may also include processing the first image in the first processing path in parallel with processing the second image in the second processing path. The first path may share processing parameters with the second path. The method may further include providing a diagnostic output based on the processing of the first image and the second image.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 16, 2022
    Assignee: KEYAMED NA, INC.
    Inventors: Feng Gao, Hao-Yu Yang, Youbing Yin, Yue Pan, Xin Wang, Junjie Bai, Yi Wu, Kunlin Cao, Qi Song
  • Patent number: 11418030
    Abstract: Fast simultaneous feasibility testing (SFT) for management of an electrical power grid is achieved through various innovations. The computation problem relates to evaluation of candidate solutions for external power flows into a power grid, with respect to predetermined constraints and contingencies. Storage and computations are reduced by formulating the problem in terms of transactional nodes (e.g. third party connections for generators and loads) instead of the larger number of bus nodes. Further advantages are achieved by precomputing matrices that can be reused across multiple SFT invocations, organizing matrices and operations to reduce storage and computation, and eliminating branches that have no contingency violations.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: August 16, 2022
    Assignee: BATTELLE MEMORIAL INSTITUTE
    Inventors: Jesse T. Holzer, Yonghong Chen, Feng Pan, Edward Rothberg
  • Patent number: 11404309
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Chang, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Patent number: D965310
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: October 4, 2022
    Inventor: Feng Pan
  • Patent number: D968154
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: November 1, 2022
    Inventor: Feng Pan