Abstract: A FRAM memory device can include a plurality of FRAM memory cells, each FRAM memory cell including one transistor and one capacitor electrically coupled to the at least one transistor. The capacitor can be configured to store a bit of data. The memory device can also include a local bit-line configured to carry data to be read from or written to the plurality of memory cells. The memory device can further include a global bit-line configured to communicate with the local bit-line to carry the data to be read from or written to the plurality of memory cells. The memory device can additionally include a local sense amplifier configured to amplify a signal in the local bit-line and transfer the amplified signal to the global bit-line based on a reference signal. The local sense amplifier can be configured to generate the amplified signal based on comparison to the reference signal.

Abstract: A FRAM memory device can include a plurality of FRAM memory cells, each FRAM memory cell including one transistor and one capacitor electrically coupled to the at least one transistor. The capacitor can be configured to store a bit of data. The memory device can also include a local bit-line configured to carry data to be read from or written to the plurality of memory cells. The memory device can further include a global bit-line configured to communicate with the local bit-line to carry the data to be read or written to the plurality of memory cells. The memory device can additionally include a local sense amplifier configured to amplify a signal in the local bit-line and transfer the amplified signal to the global bit-line based on a reference signal. The memory device can also include an amplifier or a buffer configured to provide the reference signal to drive a plurality of local sense amplifiers including the local sense amplifier.

Abstract: A system for providing dual endpoint access control of remote cloud-stored resources that includes at least one end-user entity running at least one application, the at least one application being adapted to perform at least one operation to at least one cloud-stored resource; and a local host interface configured to control access to the remote cloud-stored resources over a communication network by the at least one end-user entity running the at least one application, wherein the local host interface comprises a first access policy relating a set of authorized operations with at least one access permission to one or more of the of cloud-stored resources. Other aspects are described herein.

Abstract: A unified model for a neural network can be used to predict a particular value, such as a customer value. In various instances, customer value may have particular sub-components. Taking advantage of this fact, a specific learning architecture can be used to predict not just customer value (e.g. a final objective) but also the sub-components of customer value. This allows improved accuracy and reduced error in various embodiments.

Abstract: Polyurethane foam compositions having reduced odor and methods for producing the same are provided. The polyurethane foam compositions can include (a) a polyfunctional isocyanate; (b) an isocyanate reactive composition; and (c) an amine catalyst.

Abstract: Provided is an imageable composition for a photosensitive negative-working lithographic printing plate, and a platemaking method therefor. The imageable composition includes the following components in parts by mass: 25-65 parts of a free radical polymerizable compound, 0.5-25 parts of a photoinitiator, 10-60 parts of a binder, and 1-20 parts of a development accelerator. The platemaking method may comprise coating a substrate, which may have a hydrophilic surface or a hydrophilic layer, with an imageable composition to obtain a photosensitive negative-working lithographic printing plate precursor. The method may additionally include exposing the lithographic printing plate precursor by using laser light and according to a required image, so as to form an exposed region and an unexposed region. Further the method may include removing the unexposed region from the exposed printing plate precursor by means of a development process, so as to obtain a required lithographic printing plate.

Abstract: A method for forming a memory device is provided. An alternating dielectric stack is formed on a substrate. The alternating dielectric stack includes a dielectric layer pair, and the dielectric layer pair includes a first dielectric layer and a second dielectric layer different from the first dielectric layer. A barrier structure extending vertically through the alternating dielectric stack and laterally separating the alternating dielectric stack into a first portion and a second portion is formed. The barrier structure has an unclosed shape. The first dielectric layer in the second portion of the alternating dielectric stack is replaced with a conductor layer to form an alternating conductor/dielectric stack including the conductor layer and a third dielectric layer. A through array contact structure extending vertically through the first portion of the alternating dielectric stack to the substrate is formed.

Abstract: A FRAM memory device can include a plurality of FRAM memory cells, each FRAM memory cell including one transistor and one capacitor electrically coupled to the at least one transistor. The capacitor can be configured to store a bit of data. The memory device can also include a local bit-line configured to carry data to be read from or written to the plurality of memory cells. The memory device can further include a global bit-line configured to communicate with the local bit-line to carry the data to be read from or written to the plurality of memory cells. The memory device can additionally include a local sense amplifier configured to amplify a signal in the local bit-line and transfer the amplified signal to the global bit-line based on a reference signal. The local sense amplifier can be configured to generate the amplified signal based on comparison to the reference signal.

Abstract: A FRAM memory device can include a plurality of FRAM memory cells, each FRAM memory cell including one transistor and one capacitor electrically coupled to the at least one transistor. The capacitor can be configured to store a bit of data. The memory device can also include a local bit-line configured to carry data to be written to the plurality of memory cells. The memory device can further include a global bit-line configured to communicate with the local bit-line to carry the data to be written to the plurality of memory cells. The memory device can additionally include a local sense amplifier configured to amplify a signal from the global bit-line and to transfer the amplified signal to the local bit-line based on a reference signal. The local sense amplifier can be configured to generate the amplified signal based on comparison to the reference signal.

Abstract: A FRAM memory device can include a plurality of FRAM memory cells, each FRAM memory cell including one transistor and one capacitor electrically coupled to the at least one transistor. The capacitor can be configured to store a bit of data. The memory device can also include a local bit-line configured to carry data to be read from or written to the plurality of memory cells. The memory device can further include a global bit-line configured to communicate with the local bit-line to carry the data to be read or written to the plurality of memory cells. The memory device can additionally include a local sense amplifier configured to amplify a signal in the local bit-line and transfer the amplified signal to the global bit-line based on a reference signal. The memory device can also include an amplifier or a buffer configured to provide the reference signal to drive a plurality of local sense amplifiers including the local sense amplifier.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.

Abstract: A FRAM memory device can include a plurality of FRAM memory cells, each FRAM memory cell including one transistor and one capacitor electric-ally coupled to the at least one transistor. The capacitor can be configured to store a bit of data. The memory device can also include a local bit-line configured to carry data to be written to the plurality of memory cells. The memory device can further include a global bit-line configured to communicate with the local bit-line to carry the data to be written to the plurality of memory cells. The memory device can additionally include a local sense amplifier configured to amplify a signal from the global bit-line and to transfer the amplified signal to the local bit-line based on a reference signal. The local sense amplifier can be configured to generate the amplified signal based on comparison to the reference signal.

Abstract: To leverage an amount of unused bandwidth at a hardware encoder to generate motion estimation data, a processing unit includes a hardware encoder configured to perform a first encoding job including encoder sessions to encode a captured frame, determine motion estimation data for a rendered frame, and encode the rendered frame. Further, the processing unit includes a pre-processing circuitry configured to determine a set of motion estimation parameters based on an encoder delay associated with the performance of the first encoding job by the hardware encoder. The hardware encoder is then configured to perform a second encoding job using the determined set of motion estimation parameters.

Abstract: In an embodiment, a computer-implemented method for dynamically exchanging runtime state data between datacenters with a gateway using a controller bridge is disclosed. In an embodiment, the method comprises: receiving one or more first runtime state data from one or more logical sharding central control planes (“CCPs”) controlling one or more logical sharding hosts; receiving one or more second runtime state data from a gateway that is controlled by a CCP that also controls one or more physical sharding hosts; aggregating to aggregated runtime state data, the one or more first runtime state data received from the one or more logical sharding CCPs and the one or more second runtime state data received from the gateway; determining updated runtime state data based on the aggregated runtime state data, the one or more first runtime state data, and the one or more second runtime state data; and transmitting the updated runtime state data to at least one of the one or more logical sharding CCPs and the gateway.

Abstract: An electronic assembly comprises a housing having abase and a cover and electronic component mounted in the housing on a carrier. The carrier is pivotable about a first edge within the housing. An adjustment handle moves the carrier at a second, opposite, edge thereby to bring the electronic component into thermal contact with an internal surface of the cover after the cover is closed (or during closing of the cover), for dissipating heat from the electronic component.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.

Abstract: A three-dimensional (3D) NAND memory device includes a substrate, a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack to the substrate. The first stack is disposed on the substrate and includes first and second dielectric layers arranged alternately in a vertical direction. The second stack is disposed on the substrate and includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure has an unclosed shape.

Abstract: An encoder encodes an image portion by recursively partitioning the portion into a partitioning hierarchy of levels. The top level has a single block representing the entire portion and each lower level has four smaller blocks representing a corresponding larger block at a higher level. A palette table is generated for each bottom-level block based on the pixels of the associated block. For each successively higher level, the encoder generates a palette table for each current-level block by selecting palette colors based on the palette colors from the four palette tables for the associated four blocks at the next-lowest level. A color index map is then generated based on a final palette table selected from the palette tables generated for the partitioning hierarchy. A representation of the portion is then encoded using the final palette table and the color index map to generate a corresponding segment of an encoded bitstream.