Abstract: A new design and rapid construction method for flush assembly of prefabricated steel beams and floor slabs is disclosed. The upper flange of prefabricated steel beams is “” shaped, which consists of horizontal flange, vertical flange and top flange. Both beam stiffeners and studs are set on the horizontal flange, in which the former can strengthen the bearing capacity of the beam and avoid its local deformation, and the latter can fix the floor slab; prefabricated studs and precast concrete inside the vertical flange in the factory are used to constrain the deformation of upper flange. There is no limitation with respect to the form of floor slab, which is connected with the prefabricated steel beam by hitching the prefabricated rebar ring of the floor slab to the welded studs of the upper flange of the prefabricated steel beam.

Abstract: Systems, apparatuses, and methods for calculating multi-pass histograms for palette table derivation include an encoder that calculates a first histogram for a first portion of most significant bits (MSBs) of pixel component values of a block of an image or video frame. Then, the encoder selects a given number of the highest pixel count bins from the first histogram. The encoder then increases the granularity of these selected highest pixel count bins by evaluating one or more additional bits from the pixel component values. A second histogram is calculated for the concatenation of the original first portion MSBs from the highest pixel count bins and the one or more additional bits, and the highest pixel count bins are selected from the second histogram. A palette table is derived based on these highest pixel count bins selected from the second histogram, and the block is encoded using the palette table.

Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network and multiple host computers executing multiple machines. At a first host computer, the method identifies and stores (i) multiple time values associated with several packet processing operations performed on a particular packet sent by a first machine executing on the first host computer, and (ii) a time value associated with packet transmission through the SDDC network from the first host computer to a second host computer that is a destination of the particular packet. The method provides the stored time values to a set of one or more controllers to process to identify multiple latencies experienced by multiple packets processed in the SDDC.

Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network, several host computers executing several machines, and a set of one or more controllers. At the set of controllers, the method o receives, from a set of host computers, (i) a first set of time values associated with multiple packet processing operations performed on packets sent by a set of machines executing on the set of host computers and (ii) a second set of time values associated with packet transmission between host computers through the SDDC network. The method processes the first and second sets of time values to identify a set of latencies experienced by multiple packets processed and transmitted in the SDDC.

Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.

Abstract: A backlight source of a backlight module of a display device is divided into N*M regions. A backlight driving device includes: an MCU configured to acquire backlight data about the N*M regions corresponding to a current display image of the display device and transmit the backlight data about the N*M regions to a backlight source driving circuitry in a one-tone manner; and the backlight source driving circuitry including M PWM outputs and N registers corresponding to each PWM output. The N*M registers of the backlight source driving circuitry correspond to the N*M regions respectively. The backlight source driving circuitry is configured to receive backlight data about the N*M regions from the MCU, and write the backlight data about each region into a corresponding register, so as to control luminance of the corresponding region in accordance with the backlight data.

Abstract: Embodiments of operation methods of ferroelectric memory are disclosed. In an example, a method for reading ferroelectric memory cells is disclosed. The ferroelectric memory cells include a first set of ferroelectric memory cells and a second set of ferroelectric memory cells. In a first cycle, first data in a first ferroelectric memory cell of the first set of ferroelectric memory cells is sensed. In a second cycle subsequent to the first cycle, the sensed first data is written back to the first ferroelectric memory cell, and second data in a second ferroelectric memory cell of the second set of ferroelectric memory cells is simultaneously sensed.

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure including two parallel barrier walls extending vertically through the alternating layer stack and laterally along a word line direction to laterally separate the first region from the second region. The memory device further comprises a plurality of through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack.

Abstract: Embodiments of methods for testing three-dimensional memory devices are disclosed. The method can include: applying an input signal to a first conductive pad of the memory device by a first probe of a probe card; transmitting the input signal through the first conductive pad, a first TAC, a first interconnect structure passing through a bonding interface of the memory device, at least one of a memory array contact and a test circuit to a test structure; receiving an output signal through a second interconnect structure passing through the bonding interface, a second TAC, at least one of the memory array contact and the test circuit from the test structure; measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card; and determining a characteristic of the test structure based on the input signal and the output signal.

Abstract: Systems, apparatuses, and methods for performing parallel histogram calculation with application to palette table derivation are disclosed. An encoder calculates a first histogram for a first portion of pixel component value bits of a block of pixels. Then, the encoder selects a first number of the highest pixel count bins from the first histogram. Also, the encoder calculates a second histogram for a second portion of pixel component value bits of the block. The encoder selects a second number of the highest pixel count bins from the second histogram. A third histogram is calculated from the concatenation of bits assigned to the first and second number of bins, and the highest pixel count bins are selected from the third histogram. A palette table is derived based on these highest pixel count bins selected from the third histogram, and the block of pixels is encoded using the palette table.

Abstract: Systems, apparatuses, and methods for calculating multi-pass histograms for palette table derivation are disclosed. An encoder calculates a first histogram for a first portion of most significant bits (MSBs) of pixel component values of a block of an image or video frame. Then, the encoder selects a given number of the highest pixel count bins from the first histogram. The encoder then increases the granularity of these selected highest pixel count bins by evaluating one or more additional bits from the pixel component values. A second histogram is calculated for the concatenation of the original first portion MSBs from the highest pixel count bins and the one or more additional bits, and the highest pixel count bins are selected from the second histogram. A palette table is derived based on these highest pixel count bins selected from the second histogram, and the block is encoded using the palette table.

Abstract: A backlight, a control method of the backlight, and a display device are provided. The backlight includes a plurality of light-emitting modules arranged in an array. Each of the light-emitting modules includes a light-emitting unit and a control circuit. The control circuit includes n branches, a controller, and a current module. Each branch of the n branches is connected in series with the light-emitting unit and the current module. Each branch is provided with a switch, and the controller is separately connected to the switch on each branch.

Abstract: Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the charge pump, and a charge pump regulator circuit coupled to the charge pump. One such charge pump regulator circuit is configured to control the charge pump to increase the output voltage during a first period of time. Such a charge pump regulator circuit can also cause a node of a circuit coupled to the output node of the charge pump to reach a target voltage level during a second time period.

Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

Abstract: A backlight module, a display device and a driving method thereof are provided. The backlight module includes: a micro control circuit, a selection control circuit, a backlight source including a primary viewing region and a subsidiary viewing region, and a backlight driver chip; the micro control circuit is configured to output a selection signal to the selection control circuit and output a control signal to the backlight driver chip after a scanning of a display sub-region corresponding to the primary viewing region or the subsidiary viewing region is completed; the selection control circuit is configured to select the light-emitting components within the primary viewing region or the subsidiary viewing region according to the selection signal; and the backlight driver chip is configured to supply a drive current to the light-emitting components within the primary viewing region or the subsidiary viewing region that is selected according to the control signal.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, multiple through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack, an array interconnection layer in contact with the through array contacts, a peripheral circuit formed on a second substrate. and a peripheral interconnection layer on the peripheral circuit.

Abstract: A new design and rapid construction method for flush assembly of prefabricated steel beams and floor slabs is disclosed. The upper flange of prefabricated steel beams is “” shaped, which consists of horizontal flange, vertical flange and top flange. Both beam stiffeners and studs are set on the horizontal flange, in which the former can strengthen the bearing capacity of the beam and avoid its local deformation, and the latter can fix the floor slab; prefabricated studs and precast concrete inside the vertical flange in the factory are used to constrain the deformation of upper flange. There is no limitation with respect to the form of floor slab, which is connected with the prefabricated steel beam by hitching the prefabricated rebar ring of the floor slab to the welded studs of the upper flange of the prefabricated steel beam.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.

Abstract: The present disclosure provides a method, an apparatus, and a virtual reality device for displaying a virtual reality scene. The method comprises: acquiring pose information of a user and transmitting the pose information to a target device; receiving static picture data corresponding to the pose information transmitted by the target device through a first transmission channel and storing the static picture data; and generating a display picture according to the static picture data and displaying the display picture.