Abstract: The present invention relates to the field of manufacture of polymer materials, and more particularly to an ultra-high molecular weight polyethylene (UHMWPE) composition and a cut resistant and creep resistant fiber prepared therefrom. The ultra-high molecular weight polyethylene composition comprises the following components: modified graphene, modified silicon carbide whisker, and ultra-high molecular weight polyethylene. The ultra-high molecular weight polyethylene composition provided by the present invention has superior cut resistance, high strength and high modulus. By regulating the morphology of silicon carbide, the type of a coupling agent, the mixing ratio and so on, not only cut resistance, high strength and high modulus can be provided, but also creep resistance can be improved.

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure extended above a substrate and forming a gate structure formed over a portion of the fin structure. The method also includes forming a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The method further includes doping an outer portion of the S/D structure to form a doped region, and the doped region includes gallium (Ga). The method includes forming a metal silicide layer over the doped region; and forming an S/D contact structure over the metal silicide layer.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure protruding from a substrate and a doped region formed in the fin structure. The semiconductor structure further includes a metal gate structure formed across the fin structure and a gate spacer formed on a sidewall of the metal gate structure. The semiconductor structure further includes a source/drain structure formed over the doped region. In addition, the doped region continuously surrounds the source/drain structure and is in direct contact with the gate spacer.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

Abstract: A light source module includes a backplane, a light source, a reflective layer, a color conversion layer, and at least one optical film. The backplane has a first bottom surface, a first sidewall surface, a second bottom surface, and a second sidewall surface. The first sidewall surface is connected between the first bottom surface and the second bottom surface. The second bottom surface is higher than the first bottom surface and connected between the first sidewall surface and the second sidewall surface. The light source is disposed on the first bottom surface. The reflective layer is disposed on the second bottom surface and the second sidewall surface. The color conversion layer is disposed on the reflective layer. The at least one optical film is placed on the second bottom surface. The reflective layer and the color conversion layer are located between the at least one optical film and the backplane.

Abstract: A sacrificial layer is formed over a first channel structure of an N-type transistor (NFET) and over a second channel structure of a P-type transistor (PFET). A PFET patterning process is performed at least in part by etching away the sacrificial layer in the PFET while protecting the NFET from being etched. After the PFET patterning process has been performed, a P-type work function (WF) metal layer is deposited in both the NFET and the PFET. An NFET patterning process is performed at least in part by etching away the P-type WF metal layer and the sacrificial layer in the NFET while protecting the PFET from being etched. After the NFET patterning process has been performed, an N-type WF metal layer is deposited in both the NFET and the PFET.

Abstract: A method includes providing a structure having a first stack of nanostructures spaced vertically one from another and a second stack of nanostructures spaced vertically one from another, forming a dielectric layer wrapping around each of the nanostructures in the first and second stacks, depositing an n-type work function layer on the dielectric layer and a p-type work function layer on the n-type work function layer and over the first and second stacks. The n-type work function layer wraps around each of the nanostructures in the first stack. The p-type work function layer wraps around each of the nanostructures in the second stack. The method also includes forming an electrode layer on the p-type work function layer and over the first and second stacks.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece comprising a first channel member directly over a first region of a substrate and a second channel member directly over the first channel member, the first channel member being vertically spaced apart from the second channel member, conformally forming a dielectric layer over the workpiece, conformally depositing a dipole material layer over the dielectric layer, after the depositing of the dipole material layer, performing a thermal treatment process to the workpiece, after the performing of the thermal treatment process, selectively removing the dipole material layer, and forming a gate electrode layer over the dielectric layer.

Abstract: This application provides example data packet transmission methods and example communications apparatuses. One example method includes receiving a data packet, where the data packet is in an undelivered state. The data packet can then be delivered during running of a reordering timer upon an arrival of a first delay cut-off moment corresponding to the data packet or an arrival of a second delay cut-off moment of an additional data packet before the data packet in a reordering window.

Abstract: A coil module, power transmitting circuit and power receiving circuit are disclosed. The coil module including at least two parallel branches, wherein each parallel branch includes a coil and a first capacitor which are connected in series; the capacitances of the first capacitors are set to reduce or eliminate an equivalent impedance difference between the parallel branches. Therefore, the loss is reduced and the wireless charging efficiency is improved while ensuring the charging rate and the charging degree of freedom.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode formed over a channel region, a first gate dielectric layer is formed over the channel region in the gate space, a second gate dielectric layer is formed over the first gate dielectric layer, one or more conductive layers is formed on the second gate dielectric layer, the second gate dielectric layer and the one or more conductive layers are recessed, an annealing operation is performed to diffuse an element of the second gate dielectric layer into the first gate dielectric layer, and one or more metal layers are formed in the gate space.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A light source module includes a backplane, a light source, a reflective layer, a color conversion layer, and at least one optical film. The backplane has a first bottom surface, a first sidewall surface, a second bottom surface, and a second sidewall surface. The first sidewall surface is connected between the first bottom surface and the second bottom surface. The second bottom surface is higher than the first bottom surface and connected between the first sidewall surface and the second sidewall surface. The light source is disposed on the first bottom surface. The reflective layer is disposed on the second bottom surface and the second sidewall surface. The color conversion layer is disposed on the reflective layer. The at least one optical film is placed on the second bottom surface. The reflective layer and the color conversion layer are located between the at least one optical film and the backplane.

Abstract: Semiconductor device structure and methods of forming the same are described. The structure includes a dielectric layer disposed over an epitaxy source/drain region and a conductive feature disposed in the dielectric layer. The conductive feature includes a metal liner including a first material and a metal fill surrounded by the metal liner. The metal fill includes the first material having a first grain size. The conductive feature further includes a metal cap disposed on the metal liner and the metal fill, and the metal cap includes the first material having a second grain size different from the first grain size.

Abstract: A magnetic wireless charging holder includes a holder body and a main body. The main body is disposed on the holder body. The main body includes a housing, a wireless charging module, and a first magnet configured to attract a built-in magnet of a mobile phone. A magnetic shield is fixed in the housing for attracting and positioning the first magnet. With the first magnet, the product has a magnetic attraction function. The first magnet and the built-in magnet of the mobile phone are mutually attracted each other to achieve a rapid and accurate alignment.

Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; forming fins on the substrate; depositing a dummy gate electrode over the fins; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; performing a first treatment at a first temperature to repair defects in at least one of the dummy gate electrode, the gate spacer and the LDD region; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; depositing an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and subsequent to the forming of the replacement gate, performing a second treatment at a second temperature, lower than the first temperature, to repair defects of the semiconductor device.

Abstract: A pivoting device, including a hinge assembly and at least two support plates. The hinge assembly includes a base, two movable members on the base, at least two fixed members connecting the movable members, and two driven levers on the base and driven by the fixed members; the base has at least two rails where the movable members are provided, the movable members enable a flexible display to be folded when moving in an arc-shaped path, and the fixed members each have an oblique slot allowing one driven lever to move therein. The support plates each have a sliding rail portion at an end thereof and allowing one driven lever to slide therein, and when the driven levers are slide along the sliding rail portion and the oblique slot simultaneously, the support plates are flipped up and tilt outwards.