Abstract: A display substrate comprises a display region comprising a first display sub-region and a second display sub-region adjoining the first display sub-region, a plurality of first-type sub-pixels located in the first display sub-region that are divided into sub-pixel groups, each sub-pixel group comprising at least two adjacent first-type sub-pixels in a row direction, each first-type sub-pixel comprising a light-emitting element and a pixel circuit configured to drive the light emitting element to emit light; and a plurality of power lines connected to the first-type sub-pixels. The power lines comprise first-type and second-type power lines. The first-type power lines extend in the row direction and are connected to pixel circuits of the first-type sub-pixels in the row direction, and the second-type power lines extend in a column direction and are connected to pixel circuits of the first-type sub-pixels in the column direction. The row direction and the column direction intersect.

Abstract: Provided are a display substrate and a display apparatus. The display substrate includes a first display region and a second display region, and a pixel density of the first display region is higher than a pixel density of the second display region. A first pixel circuit of a first sub-pixel in the first display region includes one pixel circuit unit, and a second pixel circuit of a second sub-pixel in the second display region includes two pixel circuit units. The first pixel circuit is configured to be connected with a first power voltage terminal to receive a first power voltage as a pixel power voltage, and the second pixel circuit is configured to be connected with a second power voltage terminal to receive a second power voltage as a pixel power voltage and the first power voltage is different from the second power voltage.

Abstract: An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.

Abstract: A method of verifying an integrated circuit stack includes adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate. The method further includes converting the first dummy layer location to the connecting substrate. The method further includes adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad. The method further includes performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor device and a heating structure. The semiconductor substrate includes a device region and a heating region surrounding the device region. The semiconductor device is located on the device region. The heating structure is located on the heating region and includes an intrinsic semiconductor area, at least one heating element and at least one heating pad. The intrinsic semiconductor area is surrounding the semiconductor device. The at least one heating element is located at a periphery of the intrinsic semiconductor area. The at least one heating pad is joined with the at least one heating element, wherein the at least one heating pad includes a plurality of contact structures, and a voltage is supplied from the plurality of contact structures to control a temperature of the at least one heating element.

Abstract: Disclosed is a system and method for communication using an efficient fiber-to-chip grating coupler with a high coupling efficiency.

Abstract: A method and system for generating a physical layout for a grating coupler integrated in a photonically-enabled circuit are disclosed herein. In some embodiments, the method receives a parametrized wavelength, a parametrized first refractive index, a parametrized second refractive index, a parametrized taper length, a parametrized width, a parametrized grating length, and a parametrized incident angle of the optical beam incident onto the grating coupler and generates a physical layout for the grating coupler based on the received parametrized inputs, the generating of the physical layout is according to a predefined model, and outputs the physical layout of the grating coupler for manufacturing under a semiconductor fabrication process.

Abstract: The present invention discloses a diaphragm for a speaker including a lower surface area, a central area formed on said lower surface area, an upper surface area formed on said central area. The upper surface area, the central area and the lower surface area includes homogeneous amorphous materials. The diaphragm includes internal stress changing with a depth from the surface to the center of the diaphragm.

Abstract: In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.

Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Abstract: A display substrate and a display device are provided. The display substrate includes a display region and a non-display region at least partially surrounding the display region and including a binding region. A plurality of first pads are located in the binding region, and configured to be electrically coupled to an external electrical test circuitry at a panel test stage, and bound to a circuit board so as to transmit an electric signal from the circuit board to the display region at a display stage. A plurality of second pads are located in the binding region, and configured to be bound to the circuit board so as to transmit the electric signal from the circuit board to the display region at the display stage.

Abstract: A package structure includes a first die, a second die over and electrically connected to the first die, an insulating material around the second die, a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die, wherein the first antenna includes a first conductive plate extending through the insulating material, and a plurality of first conductive pillars extending through the insulating material, wherein the first conductive plate is between the plurality of first conductive pillars and the first sidewall of the second die.

Abstract: Systems and methods for suppressing and mitigating harmonic distortion in a circuit are disclosed. In one example, a disclosed circuit includes a radio frequency (RF) oscillator and a power amplifier. The RF oscillator is configured to generate an RF signal. The power amplifier is configured to generate an amplified RF signal based on the RF signal. The power amplifier includes a transformer including a primary winding and a secondary winding, and a feedback capacitor electrically coupled to the primary winding and the secondary winding.

Abstract: A display substrate is provided. The display substrate includes a base substrate and a plurality of reset signal lines. The base substrate includes a display region, the display region includes a plurality of sub-pixels arranged in array, each of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element. The plurality of reset signal lines extend in a first direction, the plurality of reset signal lines include a plurality of first reset signal lines for providing a first reset signal and a plurality of second reset signal lines for providing a second reset signal, and one of the plurality of first reset signal lines and one of the plurality of second reset signal lines are respectively connected to pixel driving circuits of a plurality of sub-pixels located in a same row.

Abstract: A package structure includes a photonic die, an electronic die and a gap filling layer. The photonic die includes a dielectric layer, a silicon layer, a reflector structure and a plurality of connection pads. The silicon layer is disposed on the dielectric layer, wherein the silicon layer includes a grating coupler having a plurality of first trench patterns with a first depth and a plurality of second trench patterns with a second depth, wherein the first depth is different than the second depth. The reflector structure is embedded in the dielectric layer below the grating coupler. The connection pads are disposed over the dielectric layer. The electronic die is disposed on the photonic die, wherein the electronic die includes a plurality of bonding pads bonded to the connection pads of the photonic die. The gap filling layer is disposed on the photonic die and surrounding the electronic die.

Abstract: A semiconductor structure including a semiconductor substrate, a first patterned dielectric layer, a grating coupler and a waveguide is provided. The semiconductor substrate includes an optical reflective layer. The first patterned dielectric layer is disposed on the semiconductor substrate and covers a portion of the optical reflective layer. The grating coupler and the waveguide are disposed on the first patterned dielectric layer, wherein the grating coupler and the waveguide are located over the optical reflective layer.

Abstract: A display substrate and a display apparatus are disclosed. The display substrate includes a base substrate including a display region and a peripheral region located on at least one side of the display region, and a first gate drive circuit, the first gate drive circuit includes a first clock signal line, a second clock signal line and N shift register units that are cascaded; each shift register unit of the N shift register units includes a first output circuit; the first output circuit includes the first output transistor, the orthographic projection of the second clock signal line on the base substrate is located between an orthographic projection of the first output transistor on the base substrate and the orthographic projection of the first clock signal line on the base substrate. The display substrate can reduce load of the first clock signal line and the second clock signal line.

Abstract: Disclosed is a system and method for communication using an efficient fiber-to-chip grating coupler with a high coupling efficiency.

Abstract: A control method of an air conditioner, includes: acquiring a temperature of injected vapor and a pressure of the injected vapor of a compressor of the air conditioner, to obtain a superheat degree of the injected vapor of the compressor of the air conditioner and a continuous duration of the superheat degree of the injected vapor; if the continuous duration is greater than or equal to a first preset value, and if an exhaust temperature of the compressor is less than a critical value of the exhaust temperature of the compressor within the continuous duration, controlling the compressor to be in a shutdown state, and if the continuous duration is less than the first preset value, and if the exhaust temperature of the compressor is less than the critical value of the exhaust temperature of the compressor within the continuous duration, controlling the compressor to remain in an operating state.