Abstract: Provided is a display substrate. In the display substrate, at least one data-select circuit group may control a data line lead to transmit a data signal to at least two data lines by time division in response to switch control signals supplied by at least two switch control lines at different time periods. A plurality of connecting portions that are electrically connected to a first power bus and a plurality of power lines may extend along the region between a plurality of the data-select circuit groups.

Abstract: A display substrate is provided. The display substrate includes a base substrate and a plurality of reset signal lines. The base substrate includes a display region, the display region includes a plurality of sub-pixels arranged in array, each of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element. The plurality of reset signal lines extend in a first direction, the plurality of reset signal lines include a plurality of first reset signal lines for providing a first reset signal and a plurality of second reset signal lines for providing a second reset signal, and one of the plurality of first reset signal lines and one of the plurality of second reset signal lines are respectively connected to pixel driving circuits of a plurality of sub-pixels located in a same row.

Abstract: A nano imprint master, an optical waveguide and method for preparing the same. The nano imprint master includes: a grating structure region; a non-grating structure region, wherein the non-grating structure region is disposed around the grating structure region; and a sinking structure, wherein the sinking structure is disposed at a position adjacent to the grating structure region in the non-grating structure region, and the sinking structure extends around a circumference of the grating structure region to surround the grating structure region.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a display region, and a non-display region surrounding the display region and including an encapsulation adhesive region surrounding the display region. The display substrate further includes an encapsulation base layer arranged at the encapsulation adhesive region; and a fanout layer arranged at the non-display region and including a first reuse portion. An orthogonal projection of the first reuse portion onto a base substrate of the display substrate at least partially overlaps an orthogonal projection of a first target region of the encapsulation adhesive region onto the base substrate, and the first reuse portion is reused as the encapsulation base layer at the first target region.

Abstract: Provided is a display panel, including: a base substrate, including a display area and a peripheral area surrounding the display area; a plurality of pixel units, disposed in the display area; a barrier structure, disposed in the peripheral area; at least one first power line, disposed in the peripheral area; and, a row drive circuit, disposed in the peripheral area, wherein orthographic projections of any two of the following structures on the base substrate are at least partially overlapped with each other: the barrier structure, the at least one first power line, and the row drive circuit.

Abstract: A Talaromyces purpureogenus and an application thereof in control of cotton diseases, a deposit number of the Talaromyces purpureogenus is CCTCCNO: M20242093. An application of the Talaromyces purpureogenus CEF642N is an application as a biocontrol agent for cotton Verticillium wilt. In the present disclosure, after analyzing the inhibitory effect of extract components of Talaromyces purpureogenus CEF642N on Verticillium dahliae, it is found that an extract of Talaromyces purpureogenus CEF642N has the effect of controlling Verticillium wilt and can be used to prepare a biocontrol agent, thereby providing a new biocontrol method for the control of Verticillium wilt.

Abstract: A display panel includes a pixel driving circuit, where the pixel driving circuit includes a driving transistor (T3) and a first transistor (T1), a first electrode of the first transistor (T1) is connected to a gate of the driving transistor (T3), a second electrode thereof is connected to a first initial signal line (Vinit1), the driving transistor (T3) is a P-type low temperature polysilicon transistor, and the first transistor (T1) is an N-type oxide transistor. The display panel further includes: a base substrate, a second conductive layer, a second active layer, a third conductive layer, and a fifth conductive layer.

Abstract: Embodiments include systems, methods, and computer-readable media for memory traffic management across a network of processing engines. An example method includes setting, at a processing engine prior to execution of a processing workload, a credit variable to an initial credit value, adding, at the processing engine during the execution of the processing workload, at a credit incrementing rate, a credit increment value to the credit variable, wherein the adding is omitted if the adding increases a current value of the credit variable above a maximum credit value, detecting, at the processing engine, a memory access request; blocking, at the processing engine, while the current value of the credit variable is less than a size of the memory access request, the memory access request, and issuing, from the processing engine, when the current value of the credit variable is equal to or greater than a size of the memory access request, the memory access request.

Abstract: A display substrate is provided. The display substrate includes a base substrate and a plurality of reset signal lines. The base substrate includes a display region, the display region includes a plurality of sub-pixels arranged in array, each of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element. The plurality of reset signal lines extend in a first direction, the plurality of reset signal lines include a plurality of first reset signal lines for providing a first reset signal and a plurality of second reset signal lines for providing a second reset signal, and one of the plurality of first reset signal lines and one of the plurality of second reset signal lines are respectively connected to pixel driving circuits of a plurality of sub-pixels located in a same row.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a display region, and a non-display region surrounding the display region and including an encapsulation adhesive region surrounding the display region. The display substrate further includes an encapsulation base layer arranged at the encapsulation adhesive region; and a fanout layer arranged at the non-display region and including a first reuse portion. An orthogonal projection of the first reuse portion onto a base substrate of the display substrate at least partially overlaps an orthogonal projection of a first target region of the encapsulation adhesive region onto the base substrate, and the first reuse portion is reused as the encapsulation base layer at the first target region.

Abstract: A display panel, a circuit board and a display device are provided, belonging to the field of displays. The display panel has a display region and a binding region which is on at least one side of the display region, and the display panel includes: a substrate; a plurality of signal pins on the substrate and in the binding region, the signal pins being arranged at intervals in a first direction and being connected to the circuit board; and at least one non-signal pin on the substrate and between two adjacent signal pins.

Abstract: A display panel includes a pixel driving circuit, where the pixel driving circuit includes a driving transistor (T3) and a first transistor (T1), a first electrode of the first transistor (T1) is connected to a gate of the driving transistor (T3), a second electrode thereof is connected to a first initial signal line (Vinit1), the driving transistor (T3) is a P-type low temperature polysilicon transistor, and the first transistor (T1) is an N-type oxide transistor. The display panel further includes: a base substrate, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer.

Abstract: A display substrate and a display device including a base substrate, a plurality of first connection wirings, and a plurality of second connection wirings. The base substrate includes a display area including a first display area and a second display area, the first display area includes a plurality of first light-emitting devices and a plurality of second light-emitting devices, and the second display area includes a plurality of first pixel circuits and a plurality of second pixel circuits. At least a portion of the plurality of first connection wirings extends along a first direction, at least a portion of the plurality of second connection wirings extends along the first direction, at least a portion of the plurality of first connection wirings is located on a first side of a row provided with first electrodes of the plurality of first and second light-emitting devices in a second direction.

Abstract: A display panel has a display area and a peripheral area surrounding the display area, and the peripheral area includes a first sub-peripheral area. A power loop line includes a sub-loop line. Each power connection line is electrically connected to the sub-loop line and a power bus. The at least two power connection lines are divided into two groups that are respectively located on two sides of a division line of the display panel. A plurality of data selectors are divided into two groups that are respectively located on the two sides of the division line. In at least one power connection line in a group and data selectors in a group that are all located on a same side of the division line, the at least one power connection line each passes through a gap between adjacent data selectors to connect the sub-loop line and the power bus.

Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes a substrate; a light-emitting functional layer disposed on the substrate; a thin-film encapsulation layer disposed on the substrate and the light-emitting functional layer and covering the light-emitting functional layer; a drying layer disposed on the substrate and disposed around the thin-film encapsulation layer; an encapsulation cover plate disposed on the drying layer and the thin-film encapsulation layer; a curing adhesive layer disposed between the substrate and the encapsulation cover plate and disposed around the drying layer, the curing adhesive layer configured to fix the substrate and the encapsulation cover plate, and a ring-shaped groove disposed around the drying layer and provided between the drying layer and the curing adhesive layer; and an encapsulant layer disposed in the ring-shaped groove.

Abstract: A display panel includes a base substrate, a second conductive portion, and first, second and fourth conductive layers located at a side of the base substrate. The first conductive layer includes a first gate line of which orthographic projection extends along a first direction and a partial structure forms a fourth transistor's gate and a first conductive portion forming a driving transistor's gate. The second conductive layer includes a second gate line of which orthographic projection extends along the first direction and is located between orthographic projections of the first conductive portion and the first gate line, and a partial structure forms a second transistor's first gate. Orthographic projection of the second conductive portion at least partially overlaps with that of the first gate line. The fourth conductive layer includes a first connection portion connected to the first and second conductive portions.

Abstract: Disclosed are a display panel and a display device. The display panel includes: a base substrate, a transistor array layer, a first planarization layer, and a first electrode layer, where the plurality of sub-pixels include first color sub-pixels and second color sub-pixels adjacent to the first color sub-pixels in a first direction; for the first color sub-pixels and the second color sub-pixels adjacent in the first direction, first notches are disposed in sides, facing orthographical projections of anodes in the first color sub-pixels on the base substrate, of orthographical projections of edges of anodes in the second color sub-pixels on the base substrate; and the first notches are disposed facing centers of main parts of the second color sub-pixels. Each repeating unit includes at least one first color sub-pixel and at least one second color sub-pixel.

Abstract: A display panel and a display device are provided. The display panel includes: a base substrate including a display region and a peripheral region; a pixel defining layer having a first part located in the display region and a second part located in the peripheral region, the second part and the first part being formed as an integral structure; and a spacer layer arranged on a side of the pixel defining layer away from the base substrate. The spacer layer includes a first spacer repetitive unit located in the display region and a second spacer repetitive unit located in the peripheral region. An orthographic projection of the second spacer repetitive unit on the base substrate falls within that of the second part on the base substrate and is located on a side, facing the display region, of a boundary, which is away from the display region, of the second part.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate has a display region and an electrode opening region, the display region includes a first electrode layer and a spacer layer on a base substrate; the electrode opening region includes a third electrode layer and a spaced insulating layer on the base substrate, the third electrode layer includes a plurality of electrode openings, the spaced insulating layer includes a plurality of insulating patterns, each insulating pattern fills a corresponding electrode opening; a maximum distance between a side of the spaced insulating layer away from the base substrate and the base substrate is a first distance, a maximum distance between a side of the spacer layer away from the base substrate and the base substrate is a second distance, a ratio of the first distance to the second distance ranges from 0.9 to 1.1.

Abstract: A display panel includes a base substrate, a second conductive portion, and first, second and fourth conductive layers located at a side of the base substrate. The first conductive layer includes a first gate line of which orthographic projection extends along a first direction and a partial structure forms a fourth transistor's gate and a first conductive portion forming a driving transistor's gate. The second conductive layer includes a second gate line of which orthographic projection extends along the first direction and is located between orthographic projections of the first conductive portion and the first gate line, and a partial structure forms a second transistor's first gate. Orthographic projection of the second conductive portion at least partially overlaps with that of the first gate line. The fourth conductive layer includes a first connection portion connected to the first and second conductive portions through a via hole.