Patents by Inventor Feng Wei

Feng Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12048135
    Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hsiu Hsu, Feng-Ming Chang, Kian-Long Lim, Ping-Wei Wang, Lien Jung Hung, Ruey-Wen Chang
  • Patent number: 12046276
    Abstract: One aspect of this description relates to a memory cell. In some embodiments, the memory cell includes a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chuan Yang, Feng-Ming Chang, Kuo-Hsiu Hsu, Ping-Wei Wang
  • Publication number: 20240242584
    Abstract: A monitoring method of tracking and recognizing based on thermal images is executed by a monitoring system. The monitoring system includes a monitoring host and a monitoring server. The monitoring host is installed in a ward room, a bathroom, a workplace, or an operation place that needs monitoring. The monitoring host utilizes an infrared camera to capture thermal image frames of care recipients, and utilizes a trained AI human detection model to analyze the thermal image frames for recognizing a motion of a human in the thermal image frames. When the motion matches a condition for generating a warning signal, the monitoring host generates and transmits the warning signal to the monitoring server. Therefore, a care provider can determine whether the care recipients have unexpected behaviors, such as falling from a bed, falling, or staying still for a long time, and can deal with it immediately.
    Type: Application
    Filed: January 16, 2023
    Publication date: July 18, 2024
    Inventors: Chin-Feng Chung, Chia-Po Wei, Chung-Hsiang Wang
  • Patent number: 12039903
    Abstract: The embodiments of the present disclosure provide a display substrate, a display panel and a manufacturing method thereof. The display substrate includes a body portion and a to-be-cut portion arranged on at least one side of the body portion, and the body portion and the to-be-cut portion are in a same plane and connected to have a one-piece structure; the display substrate further includes a plurality of test electrodes, some test electrodes are arranged on the body portion, and the other test electrodes are arranged on the to-be-cut portion. The display panel includes the body portion in the display substrate.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: July 16, 2024
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yue Long, Jianchang Cai, Feng Wei, Chao Wu
  • Patent number: 12040336
    Abstract: In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
  • Patent number: 12039011
    Abstract: An embodiment generates an initial set of training data from monitoring data. The initial set of training data is generated by combining outputs from a plurality of pretrained classifiers. The embodiment trains a new classification model using the initial set of training data to identify anomalies in monitoring data. The embodiment performs a multiple-level clustering of the data samples resulting in a plurality of clusters of sub-clusters of data samples, and generates a review list of data samples by selecting a representative data sample from each of the clusters. The embodiment receives an updated data sample from the expert review that includes a revised target classification for at least one of the data samples of the expert review list. The embodiment then trains another replacement classification model using a revised set of training data that includes the updated data sample and associated revised target classification.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: July 16, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ke Wei Wei, Jun Wang, Shuang YS Yu, Guang Ming Zhang, Yuan Feng, Yi Dai, Ling Zhuo, Jing Xu
  • Publication number: 20240232499
    Abstract: A method and system for generating a physical layout for a grating coupler integrated in a photonically-enabled circuit are disclosed herein. In some embodiments, the method receives a parametrized wavelength, a parametrized first refractive index, a parametrized second refractive index, a parametrized taper length, a parametrized width, a parametrized grating length, and a parametrized incident angle of the optical beam incident onto the grating coupler and generates a physical layout for the grating coupler based on the received parametrized inputs, the generating of the physical layout is according to a predefined model, and outputs the physical layout of the grating coupler for manufacturing under a semiconductor fabrication process.
    Type: Application
    Filed: February 16, 2024
    Publication date: July 11, 2024
    Inventors: Feng-Wei KUO, Wen-Shiang LIAO
  • Publication number: 20240233634
    Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of reset signal lines. The base substrate includes a display region which includes sub-pixels arranged in array, each sub-pixels includes a pixel driving circuit and a light-emitting element. The plurality of reset signal lines extends in a first direction and include a plurality of first reset signal lines for providing a first reset signal and a plurality of second reset signal lines for providing a second reset signal, and one of the plurality of first reset signal lines and one of the plurality of second reset signal lines are respectively connected to pixel driving circuits of a plurality of sub-pixels located in a same row. A layer where the plurality of first reset signal lines are located is different from layers where the plurality of second reset signal lines are located.
    Type: Application
    Filed: June 10, 2021
    Publication date: July 11, 2024
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kaipeng SUN, Binyan WANG, Feng WEI, Meng LI, Tianyi CHENG, Lina WANG, Cong LIU, Shiqian DAI
  • Publication number: 20240224637
    Abstract: A display panel includes a base substrate, a second conductive portion, and first, second and fourth conductive layers located at a side of the base substrate. The first conductive layer includes a first gate line of which orthographic projection extends along a first direction and a partial structure forms a fourth transistor's gate and a first conductive portion forming a driving transistor's gate. The second conductive layer includes a second gate line of which orthographic projection extends along the first direction and is located between orthographic projections of the first conductive portion and the first gate line, and a partial structure forms a second transistor's first gate. Orthographic projection of the second conductive portion at least partially overlaps with that of the first gate line. The fourth conductive layer includes a first connection portion connected to the first and second conductive portions through a via hole.
    Type: Application
    Filed: June 10, 2021
    Publication date: July 4, 2024
    Inventors: Binyan WANG, Feng WEI, Tianyi CHENG, Meng LI
  • Patent number: 12028668
    Abstract: A sound wave transducer is provided. The sound wave transducer includes a first board, a spacer layer and a second board over the first board and the spacer layer. The first board includes a carrier, a first substrate layer and a first metal layer. The carrier has a first opening formed in a central region. The first substrate layer is disposed on the carrier and over the first opening. The first metal layer is disposed on the first substrate layer. The spacer layer is disposed on the first board and surrounds the central region. The second board includes a second substrate layer, a second metal layer disposed on the spacer layer, and a plurality of second openings penetrating through the second substrate layer and the second metal layer.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: July 2, 2024
    Assignee: GLASS ACOUSTIC INNOVATIONS TECHNOLOGY CO., LTD.
    Inventors: Hsiao-Yi Lin, Kwun Kit Chan, Yi Feng Wei, Yao-Sheng Chou
  • Patent number: 12027478
    Abstract: A method of forming a semiconductor structure includes forming a first redistribution structure including a first conductive pattern. The method further includes placing a die over the first redistribution structure. The method further includes disposing a molding material over the first redistribution structure to surround the die. The method further includes removing a portion of the molding material to form an opening. The method further includes disposing a dielectric material into the opening to form a dielectric member. The method further includes forming a second redistribution structure over the molding material and the dielectric member, wherein the second redistribution structure includes an antenna structure over the dielectric member and electrically connected to the die.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao
  • Publication number: 20240210628
    Abstract: A device for optical signal processing includes a first layer, a second layer and a waveguiding layer. A lens is disposed within the first layer and adjacent to a surface of the first layer. The second layer is underneath the first layer and adjacent to another surface of the first layer. The waveguiding layer is located underneath the second layer and configured to waveguide a light beam transmitted in the waveguiding layer. A grating coupler is disposed over the waveguiding layer. The lens is configured to receive, from one of the grating coupler or a light-guiding element, the light beam, and focus the light beam towards another one of the light-guiding element or the grating coupler.
    Type: Application
    Filed: March 7, 2024
    Publication date: June 27, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei KUO, Hsing-Kuo HSIA, Chewn-Pu JOU
  • Publication number: 20240210617
    Abstract: A thermally tunable waveguide including an optical waveguide and a heater is provided. The optical waveguide includes a phase shifter. The heater is disposed over the optical waveguide. The heater includes a heating portion, pad portions and tapered portions. The heating portion overlaps with the phase shifter of the optical waveguide. The pad portions are disposed aside of the heating portion. Each of the pad portions is connected to the heating portion through one of the tapered portions respectively.
    Type: Application
    Filed: March 7, 2024
    Publication date: June 27, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei KUO, Wen-Shiang Liao
  • Publication number: 20240210619
    Abstract: A device includes a dielectric layer, a plurality of grating structures, and a dielectric material between the plurality of grating structures and on top of the plurality of grating structures. The grating structures are arranged on the dielectric layer and separated from each other, the plurality of grating structures each having a bottom portion and top portion, the top portion having a first width and the bottom portion having a second width, the second width being larger than the first width.
    Type: Application
    Filed: March 6, 2024
    Publication date: June 27, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei KUO, Chewn-Pu JOU, Hsing-Kuo Hsia
  • Publication number: 20240213261
    Abstract: A display panel includes a pixel driving circuit, where the pixel driving circuit includes a driving transistor (T3) and a first transistor (T1), a first electrode of the first transistor (T1) is connected to a gate of the driving transistor (T3), a second electrode thereof is connected to a first initial signal line (Vinit1), the driving transistor (T3) is a P-type low temperature polysilicon transistor, and the first transistor (T1) is an N-type oxide transistor. The display panel further includes: a base substrate, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer.
    Type: Application
    Filed: June 10, 2021
    Publication date: June 27, 2024
    Inventors: Feng WEI, Binyan WANG, Tianyi CHENG, Meng LI
  • Patent number: 12018981
    Abstract: A device includes a scattering structure and a collection structure. The scattering structure is arranged to concurrently scatter incident electromagnetic radiation along a first scattering axis and along a second scattering axis. The first scattering axis and the second scattering axis are non-orthogonal. The collection structure includes a first input port aligned with the first scattering axis and a second input port aligned with the second scattering axis. A method includes scattering electromagnetic radiation along a first scattering axis to create first scattered electromagnetic radiation and along a second scattering axis to create second scattered electromagnetic radiation. The first scattering axis and the second scattering axis are non-orthogonal. The first scattered electromagnetic radiation is detected to yield first detected radiation and the second scattered electromagnetic radiation is detected to yield second detected radiation.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chewn-Pu Jou, Feng Wei Kuo, Huan-Neng Chen, Lan-Chou Cho
  • Publication number: 20240201439
    Abstract: A semiconductor package and a manufacturing method thereof are provided. A die stack in the semiconductor package includes a photonic die and an electronic die stacked on the photonic die by a face-to-face manner. A convex lens is disposed at a back surface of the electronic die, and is formed in an oval shape, such that optical beams can be collimated to have circular beam shape, as passing through the convex lens. In some embodiments, the semiconductor package includes more of the die stacks, and includes an interposer lying below the die stacks. In these embodiments, tilted reflectors are formed in the photonic dies and the interposer, to set up vertical optical paths between the interposer and the photonic dies, and lateral optical paths in the interposer. In this way, optical communication between the photonic dies can be established.
    Type: Application
    Filed: February 8, 2023
    Publication date: June 20, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei KUO, Wen-Shiang Liao
  • Publication number: 20240203330
    Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. In the display substrate, each signal line includes a first conductive portion; for at least one signal line, the display substrate includes a multi-layer insulating pattern on a side of the first conductive portion away from the base substrate; a first insulating pattern in the multi-layer insulating pattern includes a hollow, and an orthographic projection of the hollow on the base substrate is at least partially in a region surrounded by an orthographic projection of the first conductive portion on the base substrate; and for at least one clock signal line included in the at least one signal line, a ratio between a size of the hollow in a first direction and a size of a shift register unit in the first direction ranges from ¾ to 1.
    Type: Application
    Filed: February 29, 2024
    Publication date: June 20, 2024
    Applicants: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Cong LIU, Binyan WANG, Tianyi CHENG, Feng WEI, Meng LI, Shiqian DAI, Kaipeng SUN
  • Publication number: 20240194101
    Abstract: A display substrate and a display device are provided. The display substrate includes a display region and a non-display region at least partially surrounding the display region and including a binding region. A plurality of first pads are located in the binding region, and configured to be electrically coupled to an external electrical test circuitry at a panel test stage, and bound to a circuit board so as to transmit an electric signal from the circuit board to the display region at a display stage. A plurality of second pads are located in the binding region, and configured to be bound to the circuit board so as to transmit the electric signal from the circuit board to the display region at the display stage.
    Type: Application
    Filed: June 1, 2021
    Publication date: June 13, 2024
    Applicants: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE Technology Group Co., Ltd.
    Inventors: Lili Du, Hongjun Zhou, Feng Wei
  • Publication number: 20240196655
    Abstract: A display panel and a display device are provided. The display panel includes: a base substrate including a display region and a peripheral region; a pixel defining layer having a first part located in the display region and a second part located in the peripheral region, the second part and the first part being formed as an integral structure; and a spacer layer arranged on a side of the pixel defining layer away from the base substrate. The spacer layer includes a first spacer repetitive unit located in the display region and a second spacer repetitive unit located in the peripheral region. An orthographic projection of the second spacer repetitive unit on the base substrate falls within that of the second part on the base substrate and is located on a side, facing the display region, of a boundary, which is away from the display region, of the second part.
    Type: Application
    Filed: May 31, 2021
    Publication date: June 13, 2024
    Inventors: Feng Wei, Ming Hu, Hongjun Zhou, Lili Du, Cong Liu