Abstract: The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

Abstract: A semiconductor structure includes a substrate and a metal layer disposed in the substrate. The semiconductor structure includes a dielectric layer disposed over the metal layer. The semiconductor structure further includes a semiconductor layer disposed over the dielectric layer, where the metal layer extends across the semiconductor layer. The semiconductor layer includes a two-dimensional grating coupler including a plurality of scattering elements disposed in the semiconductor layer and a pair of tapered structures extending laterally from the two-dimensional grating coupler.

Abstract: The present disclosure provides a display substrate, a manufacturing method and a display device. The display substrate includes a display region, and a non-display region surrounding the display region and including an encapsulation adhesive region surrounding the display region. The display substrate further includes an encapsulation base layer arranged at the encapsulation adhesive region; and a fanout layer arranged at the non-display region and including a first reuse portion. An orthogonal projection of the first reuse portion onto a base substrate of the display substrate at least partially overlaps an orthogonal projection of a first target region of the encapsulation adhesive region onto the base substrate, and the first reuse portion is reused as the encapsulation base layer at the first target region.

Abstract: A semiconductor structure including a semiconductor substrate, a first patterned dielectric layer, a grating coupler and a waveguide is provided. The semiconductor substrate includes an optical reflective layer. The first patterned dielectric layer is disposed on the semiconductor substrate and covers a portion of the optical reflective layer. The grating coupler and the waveguide are disposed on the first patterned dielectric layer, wherein the grating coupler and the waveguide are located over the optical reflective layer.

Abstract: Systems and methods are provided for an integrated chip. An integrated chip includes a package substrate including a plurality of first layers and a plurality of second layers, each second layer being disposed between a respective adjacent pair of the first layers. A transceiver unit is disposed above the package substrate. A waveguide unit including a plurality of waveguides having top and bottom walls formed in the first layers of the package substrate and sidewalls formed in the second layers of the package substrate.

Abstract: The present invention provides a PTX3 monoclonal antibody or antibody Fab fragment thereof and use thereof. The aforementioned monoclonal antibody or antibody Fab fragment thereof specifically inhibit or slow down the binding of PTX3 to the PTX3 receptor, and may be used for a kit and method for detecting PTX3, and a pharmaceutical composition which inhibits or slows down diseases or symptoms associated with PTX3 and PTX3 receptor binding, and a use thereof.

Abstract: A display substrate includes: a base substrate having a display region and a peripheral region surrounding the display region; a plurality of sub-pixels in the display region; a plurality of data lines in the display region, electrically coupled to the plurality of sub-pixels respectively, and configured to provide a data signal to the plurality of sub-pixels respectively; a plurality of pads in the peripheral region, wherein at least a portion of the plurality of pads are configured to provide a data signal to the plurality of data lines respectively; at least one test data signal line in the peripheral region; at least one test control signal line in the peripheral region; and a plurality of test units in the peripheral region and on a side of the plurality of pads away from the display region.

Abstract: An optical device includes a waveguide configured to guide light, a taper integrated with the waveguide on a substrate configured for optical coupling, and an attenuator to degrade unwanted optical signal from the taper. The attenuator extends along one side of the taper, and includes one of a conductive structure, a doped structure and a refractive structure.

Abstract: A semiconductor device includes a silicon substrate having a first region and a second region. The semiconductor device includes a silicon lens formed in the first region and along a surface of the silicon substrate on a first side of the silicon substrate. The semiconductor device includes a photonic die disposed in the first region and on a second side of the silicon substrate, the second side being opposite to the first side. The semiconductor device includes a waveguide disposed on the second side of the silicon substrate and having a grating coupler.

Abstract: A grating coupler integrated in a photonically-enabled circuit and a method for fabricating the same are disclosed herein. In some embodiments, the grating coupler includes a substrate comprising a silicon wafer, a first grating region etched iton the substrate, wherein the first grating region comprises a first plurality of gratings having a first predetermined height, and a second grating region etched into the substrate, wherein the second grating region comprises a second plurality of gratings having a second predetermined height and wherein the first and second predetermined heights are not identical.

Abstract: An optical modulator includes a waveguide. The waveguide includes a first optical coupling region, a first electrical coupling region, and a first plurality of regions. The first optical coupling region is doped with first dopants. The first electrical coupling region is doped with the first dopants. The first plurality of regions are doped with the first dopants and are sandwiched between the first optical coupling region and the first electrical coupling region. The first plurality of regions have respective decreasing doping concentrations as distances of the first plurality of regions increase from the first electrical coupling region. The first plurality of regions have respective decreasing heights as the distances of the first plurality of regions increase from the first electrical coupling region. A maximum doping concentration of the first plurality of regions is smaller than a doping concentration of the first electrical coupling region.

Abstract: A grating coupler integrated in a photonically-enabled circuit and a method for fabricating the same are disclosed herein. In some embodiments, the grating coupler includes a substrate comprising a silicon wafer, a first grating region etched into the substrate, wherein the first grating region comprises a first plurality of gratings having a first predetermined height, and a second grating region etched into the substrate, wherein the second grating region comprises a second plurality of gratings having a second predetermined height and wherein the first and second predetermined heights are not identical.

Abstract: A semiconductor package is provided. The semiconductor package includes a photonic package that includes an electronic die and a photonic die bonded to each other. The photonic die includes a plurality of waveguides, each laterally surrounded by a respective dielectric layer, and a first redistribution structure disposed over the waveguides and the dielectric layers. At least one of the waveguides includes a meandering portion, the meandering portion includes two straight segments and a bend segment with a gradual curvature.

Abstract: Disclosed are apparatuses for optical coupling and a system for communication. In one embodiment, an apparatus for optical coupling including a substrate and a grating coupler is disclosed. The grating coupler is disposed on the substrate and includes a plurality of coupling gratings arranged along a first direction, wherein effective refractive indices of the plurality of coupling gratings gradually decrease along the first direction.

Abstract: Disclosed are apparatuses for optical coupling and a system for communication. In one embodiment, an apparatus for optical coupling having an optical coupling region is disclosed. The apparatus for optical coupling includes a substrate and a core layer disposed on the substrate. The core layer includes a plurality of holes located in the optical coupling region. An effective refractive index of the core layer gradually decrease from a first end of the optical coupling region to a second end of the optical coupling region.

Abstract: The present invention discloses a glass diaphragm having a functional layer which is selected from one of the following group or the combination thereof: explosion-proof layer, decorative layer, waterproof layer, and anti-reflection layer. The anti-explosion layer is made of PU, PVB, PC, PET or PMMA, the decorative layer contains ink materials, and the anti-reflection layer includes porous or raised structures formed by nanometer materials. The functional layer is formed by coating, spraying, pasting, ink jetting, coating.

Abstract: An integrated optical device includes a substrate, a waveguide structure and a grating structure. The substrate has a waveguide region and a grating region adjacent to each other. The waveguide structure is disposed on the substrate in the waveguide region. The grating structure is disposed on the substrate in the grating region. In some embodiments, the grating structure includes grating bars and grating intervals arranged alternately, and widths of the grating bars of the grating structure are varied.

Abstract: An optical coupler is provided. The optical coupler includes: a first optical structure, and a second optical structure disposed over the first optical structure. The first optical structure includes: a first substrate, a first cladding layer disposed on the first substrate, and a first waveguide disposed on the first cladding layer. The first waveguide includes a first coupling portion, and the first coupling portion including a first taper part. The second optical structure includes: a second substrate, a dielectric layer disposed on the second substrate; and a second waveguide disposed on the dielectric layer. The second waveguide includes a second coupling portion, and the second coupling portion including a second taper part. The second taper part is disposed on and optically coupled with the first taper part, and a taper direction of the first taper part is the same as a taper direction of the second taper part.

Abstract: A method of fabricating a package structure includes forming a photonic die, an electronic die and a gap filling layer. The photonic die includes a dielectric layer, a silicon layer, a reflector structure and connection pads. The silicon layer is disposed on the dielectric layer, wherein the silicon layer includes a grating coupler having a plurality of first trench patterns with a first depth and a plurality of second trench patterns with a second depth, wherein the first depth is different than the second depth. The reflector structure is embedded in the dielectric layer below the grating coupler. The connection pads are disposed over the dielectric layer. The electronic die is disposed on the photonic die, wherein the electronic die includes bonding pads bonded to the connection pads of the photonic die. The gap filling layer is disposed on the photonic die and surrounding the electronic die.

Abstract: The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.