Abstract: A titanium-based composite catalyst for polyester synthesis, preparation method and application thereof are provided. The preparation method is: preparing a titanium-silicon catalyst precursor first, adding the titanium-silicon catalyst precursor to a biochar material in a certain mass ratio and mixing evenly, and aging, drying, calcining and wet grinding to obtain a titanium-silicon composite catalyst, and then mixing the titanium-silicon composite catalyst and a phosphate ester with a mass ratio of 1:(0.001-0.5) to obtain the titanium-based composite catalyst. The titanium-based composite catalyst is composed of the phosphate ester and the titanium-silicon composite catalyst, wherein the phosphate ester is adsorbed and wrapped on the surface of the titanium-silicon composite catalyst; the phosphate ester is combined with a titanium-silicon catalyst in the titanium-silicon composite catalyst by van der Waals force.

Abstract: Integrated circuit structures having reduced local layout effects, and methods of fabricating integrated circuit structures having reduced local layout effects, are described. For example, an integrated circuit structure includes an NMOS region including a first plurality of fin structures or vertical stacks of horizontal nanowires, and first alternating gate lines and trench contact structures over the first plurality of fin structures or vertical stacks of horizontal nanowires. The integrated circuit structure also includes a PMOS region including a second plurality of fin structures or vertical stacks of horizontal nanowires, and second alternating gate and trench contact structures over the second plurality of fin structures or vertical stacks of horizontal nanowires. A gate line is shared between the NMOS region and the PMOS region, and a trench contact structure is shared between the NMOS region and the PMOS region.

Abstract: Embodiments disclosed herein include glass core package substrates with a stiffener. In an embodiment, an apparatus comprises a substrate with a first layer with a first width, where the first layer is a glass layer, a second layer under the first layer, where the second layer has a second width that is smaller than the first width, and a third layer over the first layer, where the third layer has a third width that is smaller than the first width. In an embodiment, the apparatus further comprises a metallic structure with a first portion and a second portion, where the first portion is over a top surface of the substrate and the second portion extends away from the first portion and covers at least a sidewall of the first layer.

Abstract: Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. Removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.

Abstract: Techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. In one such example, a FET (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction. Airgaps are provided in the regions between the gate structures and the adjacent source/drain contacts. The airgaps have a low dielectric constant (e.g., around 1.0) to reduce the parasitic capacitance between the conductive structures.

Abstract: Disclosed are a method and a device for identifying full-section excavation parameters of large-section tunnel with broken surrounding rock, which is capable of solving the problem of inaccurate arrangement of blasting hole points in tunnel excavation engineering, including following steps: establishing a three-dimensional finite element model based on a blasting section design of a tunnel; performing a simulation with the three-dimensional finite element model based on blasting design parameters to obtain blasting quality parameters; selecting a group closest to a preset quality parameter from multiple groups of the blasting design parameters as target blasting design parameters, wherein the preset quality parameter is an acceptance grade standard of the tunnel; obtaining first thermal imaging information of a first hot spot of a surface to be blasted; calibrating actual hole spacing parameters based on the first thermal imaging information and the target blasting design parameters.

Abstract: Systems, methods, and devices for offloading best path computations in a networked computing environment. A method includes storing in memory, by a best path controller, a listing of a plurality of paths learnt by a device, wherein each of the plurality of paths is a route for transmitting data from the device to a destination device. The method includes receiving, by the best path controller, a message from the device. The method includes processing, by the best path controller, a best path computation to identify one or more best paths based on the message such that processing of the best path computation is offloaded from the device to the best path controller. The method includes sending the one or more best paths to the device.

Abstract: The provided is an on-time generator circuit and a switching converter. The on-time generator circuit includes a ramp module configured to generate a ramp signal based on a drive signal of a main power transistor and an input voltage; a compensation module configured to generate a compensation signal based on the input voltage and a duty cycle; and a timing signal generation module configured to generate a timing signal based on the ramp signal, the compensation signal, and an output feedback signal. The compensation signal is used to offset delay time generated by the timing signal, making turn-on time (Ton) be preset Ton corresponding to the duty cycle, and keeping a switching frequency constant at different duty cycles.

Abstract: Some embodiments of the present disclosure provide electric heating devices and methods for kilns of substrate glass, relating to the field of arrangements of electric heating structures for the kilns of substrate glass. To address the problem of insufficient melting in front zones of kilns of high-generation and large-tonnage substrate glass, a heating structure combining side-stack tin oxide electrode bricks and bottom-inserted molybdenum electrodes is designed. A comprehensive thermal efficiency of the kiln is determined by introducing an appropriate amount of gas and determining an energy consumption of glass melting and a thermal energy contribution of gas and electricity under an extraction volume. This leads to a novel electric heating device for the kiln of high-generation and large-feeding substrate glass and a method thereof, effectively solving the problem of insufficient melting and unstable convection in the front zone of the kiln.

Abstract: An optical module including: a circuit board; an optical emission component including an emission base embedded in a mounting hole of the circuit board, a light emitting assembly disposed on the emission base and connected to the circuit board through wire bonding to generate 2N paths of optical signals, wherein N?1, and a collimating lens group located in output optical path of the light emitting assembly; a first optical reception component disposed on the circuit board to receive N paths of optical signals; a second optical reception component disposed on the circuit board to receive N paths of optical signals; an optical transmission assembly comprising a first optical fiber connected to the optical emission component, a second optical fiber connected to the first optical reception component, and a third optical fiber connected to the second optical reception component.

Abstract: In some examples, a peripheral circuit is configured to: when performing a first read operation on memory cells coupled to a selected word line, apply a first pass voltage to a first word line, apply a second pass voltage to a second word line, and apply a third pass voltage to a third word line, wherein the first word line comprises at least one word line physically located above and below the selected word line respectively, both the second word line and the third word line comprise word lines physically located on a side of the first word line away from the selected word line, memory cells coupled to the second word line comprise programmed memory cells, memory cells coupled to the third word line comprise unprogrammed memory cells, and the first pass voltage, the second pass voltage and the third pass voltage are all different.

Abstract: Devices and methods for measuring erosion resistance of electrofused high zirconia bricks are provided. The devices include a crucible, a crucible cover, a positioning axis, a plurality of holes, and a plurality of fixing members. The crucible cover is installed on an opening of the crucible, the positioning axis is installed at a center of the crucible cover, the plurality of holes are uniformly disposed along a circumferential direction of the crucible cover, and the plurality of fixing members are installed on the plurality of holes.

Abstract: Techniques to form semiconductor devices can include one or more via structures having substrate taps. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). The gate structure may extend over the semiconductor regions of any number of devices along a given direction. The gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure and includes a conductive core. The via structure has a conductive foot portion beneath the gate structure and a conductive arm portion extending from the conductive foot portion along a height of the gate structure. The conductive foot portion has a greater width along the given direction than any part of the conductive arm portion. The via structure may further include one or more dielectric layers between the conductive arm portion and the gate structure.

Abstract: Systems and methods for suppressing and mitigating harmonic distortion in a circuit are disclosed. In one example, a disclosed circuit includes a radio frequency (RF) oscillator and a power amplifier. The RF oscillator is configured to generate an RF signal. The power amplifier is configured to generate an amplified RF signal based on the RF signal. The power amplifier includes a transformer including a primary winding and a secondary winding, and a feedback capacitor electrically coupled to the primary winding and the secondary winding.

Abstract: Integrated circuit structures having patch spacers, and methods of fabricating integrated circuit structures having patch spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. An external gate spacer is along sides of the gate structure and over the stack of horizontal nanowires, the external gate spacer having one or more patch spacers therein.

Abstract: The present disclosure may provide a coil assembly. The coil assembly may include a supporting assembly and a radio frequency (RF) coil supported on the supporting assembly. The RF coil may have a plurality of coil units and a plurality of transmission ports. At least one of the plurality of transmission ports may be operably connected to a single coil unit of the plurality of coil units. Each of the plurality of transmission ports may be configured to transmit a drive signal to one of the plurality of coil units for generating a magnetic field.

Abstract: Disclosed is separation process of valuable metals from copper anode slime based on oxidation potential modulation, belonging to the technical field of industrial solid waste resource utilization. The differences in redox properties of different metal elements are used to precisely regulate the oxidation potential and acidity of the leaching solution by regulating the amount of oxidizing agent and acid added, so as to selectively and graded leaching and separating the copper (Cu), selenium (Se), tellurium (Te), and silver (Ag) metal elements, and the oxidants used are substances such as H2O2, O2 and O3.

Abstract: Disclosed is a text classification method and a text classification device. The text classification method includes: receiving text data (S1), the text data comprising one or more text semantic units; replacing the text semantic unit with a corresponding text keyword (S2), based on a correspondence between text semantic elements and text keywords; extracting, with a semantic model, a semantic feature of the text keyword (S3); and classifying, with a classification model, the text keyword at least based on the semantic feature, as a classification result of the text data (S4).

Abstract: The present application provides a processing method of a metal composite structure including a first metal layer and a second metal layer stacked on the first metal layer. The processing method includes the steps of defining a first through hole in the first metal layer, and drilling in the first through hole toward the second metal layer to form a traction hole in the second metal layer. Then, hot melt drilling is performed on a surface of the second metal layer away from the first metal layer toward the first through hole, thereby causing the second metal layer to crack under a traction force of the traction hole to form a second through hole, and a portion of the second metal layer to be melted and squeezed to form a bushing which adheres to at least a portion of a sidewall of the first through hole.

Abstract: A tiled apparatus is provided by the present disclosure. at least two of the tiled apparatus include display panels, backlight modules and lens parts. the display panel includes a display part and a tiled part. The tiled part is composed of transparent materials. An orthographic projection of the backlight module on the display panel covers the display part and at least a part of the tiled part. The lens part is disposed on a side of the display panel away from the backlight module and covers adjacent two tiled parts and a seam. The lens part partially overlaps with display parts of adjacent two display panels.