Patents by Inventor Feng Yang

Feng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230027804
    Abstract: A micro light-emitting display device having multiple display regions is provided. The micro light-emitting display device includes a substrate, multiple micro light-emitting elements, and multiple first light-emitting auxiliary structures. The micro light-emitting elements are disposed on the substrate, and positions of the micro light-emitting elements define ranges of the display regions. The micro light-emitting elements have a same first pitch between each other in any one of the display regions. The micro light-emitting elements have a second pitch between each other at a boundary across any two adjacent display regions. The first pitch is different from the second pitch. The light-emitting auxiliary structures are respectively disposed on the micro light-emitting elements. The light-emitting auxiliary structures have a same third pitch between each other.
    Type: Application
    Filed: January 18, 2022
    Publication date: January 26, 2023
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Bo-Wei Wu, Hsiang-Wen Tang, Yu-Yun Lo, Shiang-Ning Yang, Chang-Feng Tsai
  • Publication number: 20230024259
    Abstract: A wafer backside defect detection method and a wafer backside defect detection apparatus are provided. The wafer backside defect detection method includes the following steps. A peripheral edge area of a wafer backside image that at least one notch is located is cropped off. Adjacent white pixels on the wafer backside image are connected to obtain a plurality of abnormal regions. If a total area of top N of the abnormal regions is more than 10% of an area of the wafer, it is deemed that the wafer has a roughness defect. N is a natural number. If the total area of the top N of the abnormal regions is less than 1% of the area of the wafer and a largest abnormal region of the abnormal regions is longer than a predetermined length, it is deemed that the wafer has a scratch defect.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 26, 2023
    Inventors: Cheng-Hsien CHEN, Chia-Feng HSIAO, Chung-Hsuan WU, Chen-Hui HUANG, Nai-Ying LO, En-Wei TSUI, Yung-Yu YANG, Chen-Hsuan HUNG
  • Publication number: 20230025937
    Abstract: Methods of depositing platinum group metal films of high purity, low resistivity, and good conformality are described. A platinum group metal film is formed in the absence of an oxidant. The platinum group metal film is selectively deposited on a conductive substrate at a temperature less than 200° C. by using an organic platinum group metal precursor.
    Type: Application
    Filed: September 29, 2022
    Publication date: January 26, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Yixiong Yang, Wei V. Tang, Seshadri Ganguli, Sang Ho Yu, Feng Q. Liu, Jeffrey W. Anthis, David Thompson, Jacqueline S. Wrench, Naomi Yoshida
  • Publication number: 20230025527
    Abstract: Embodiments of the present disclosure provide a quantitative method and system for attention based on a line-of-sight estimation neural network, which improves the stability and training efficiency of the line-of-sight estimation neural network. A few-sample learning method is applied to training of the line-of-sight estimation neural network, which improves generalization performance of the line-of-sight estimation neural network. A nonlinear division method for small intervals of angles of the line of sight is provided, which reduces an estimation error of the line-of-sight estimation neural network. Eye opening and closing detection is added to avoid the line-of-sight estimation error caused by an eye closing state. A method for solving a landing point of the line of sight is provided, which has high environmental adaptability and can be quickly used in actual deployment.
    Type: Application
    Filed: February 25, 2022
    Publication date: January 26, 2023
    Inventors: YONGDUAN SONG, FENG YANG, RUI LI, QIN CHEN, SHICHUN WANG, HONGYU XIA, CAISHI HE, SHIHAO PU
  • Publication number: 20230027406
    Abstract: A method of manufacturing an array substrate, includes: providing a substrate; forming a gate conductive layer including at least one first alignment mark; forming a source-drain conductive thin film; aligning a first mask and the substrate on which the gate conductive layer and the source-drain conductive thin film have been formed according to the at least one first alignment mark; patterning the source-drain conductive thin film by using the first mask to form at least one second alignment mark to obtain a source-drain conductive layer; forming a black matrix thin film; aligning a second mask and the substrate on which the gate conductive layer, the source-drain conductive layer and the black matrix thin film have been formed according to the at least one second alignment mark; patterning the black matrix thin film by using the second mask to form a black matrix; and forming a color filter layer.
    Type: Application
    Filed: May 12, 2021
    Publication date: January 26, 2023
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yan WANG, Yanqing CHEN, Wei LI, Ning WANG, Weida QIN, Zhao ZHANG, Jing LI, Feng YANG
  • Publication number: 20230023611
    Abstract: A method of identifying characters in images extracts features of a detection image including characters. Enhancement processing is performed on the detection image according to the features to obtain an enhanced image. Closed edges of the characters are detected in the enhanced image. First rectangular outlines of the characters are determined according to the closed edges. The first rectangular outlines are corrected to obtain second rectangular outlines. The characters are cropped from the detection image according to the second rectangular outlines. The method identifies characters in images accurately and rapidly.
    Type: Application
    Filed: May 18, 2022
    Publication date: January 26, 2023
    Inventors: CHENG-FENG WANG, LI-CHE LIN, HUI-XIAN YANG
  • Publication number: 20230019250
    Abstract: The present disclosure generally relates to methods and user interfaces for authentication, including providing authentication at a computer system in accordance with some embodiments.
    Type: Application
    Filed: April 28, 2022
    Publication date: January 19, 2023
    Inventors: SungChang LEE, Bowen CHENG, Yue HANG, Weiqi PAN, Yue SHEN, Xiaoguang YANG, Xiaofeng YU, Feng ZHANG, Liang ZHAO, Qiuji ZHAO, Wendong ZHONG
  • Publication number: 20230011792
    Abstract: The present disclosure provides a method of forming an interconnect structure. The method includes forming a metal layer over a substrate, the metal layer including a first metal; forming a capping layer on the metal layer; patterning the capping layer and the metal layer, thereby forming trenches in the metal layer; depositing a first dielectric layer in the trenches; removing the capping layer, resulting in the first dielectric layer protruding from a top surface of the metal layer; depositing a second dielectric layer over the first dielectric layer and the metal layer; forming an opening in the second dielectric layer, thereby partially exposing the top surface of the metal layer; and forming a conductive feature in the opening and in electrical coupling with the metal layer, the conductive feature including a second metal.
    Type: Application
    Filed: July 9, 2021
    Publication date: January 12, 2023
    Inventors: Cai-Ling Wu, Hsiu-Wen Hsueh, Chii-Ping Chen, Po-Hsiang Huang, Chi-Feng Lin, Neng-Jye Yang
  • Publication number: 20230009961
    Abstract: The present invention relates to a graphic-blockchain-orientated sharding storage apparatus, at least comprising a first sharding module and a second sharding module, wherein the first sharding module shards nodes having different resource capacity levels based on ledger data organized using a DAG structure, and the second sharding module assigns transactions to the shards matching with execution difficulty levels of the transactions, so that each said transaction is processed and stored in the shard corresponding thereto. The present invention incorporates the sharding technology into a graphic blockchain to provide a graphic-blockchain-orientated sharding storage method, so as to reduce pressure in terms of data storage and transaction processing on nodes of the graphic blockchain system.
    Type: Application
    Filed: June 13, 2022
    Publication date: January 12, 2023
    Inventors: Jiang XIAO, Feng CHENG, Junpei NI, Wenhui YANG, Hai JIN
  • Publication number: 20230010160
    Abstract: Disclosed are a method for processing multimodal data using a neural network, a device, and a medium, and relates to the field of artificial intelligence and, in particular to multimodal data processing, video classification, and deep learning. The neural network includes: an input subnetwork configured to receive the multimodal data to output respective first features of a plurality of modalities; a plurality of cross-modal feature subnetworks, each of which is configured to receive respective first features of two corresponding modalities to output a cross-modal feature corresponding to the two modalities; a plurality of cross-modal fusion subnetworks, each of which is configured to receive at least one cross-modal feature corresponding to a corresponding target modality and other modalities to output a second feature of the target modality; and an output subnetwork configured to receive respective second features of the plurality of modalities to output a processing result of the multimodal data.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 12, 2023
    Inventors: Shuai CHEN, Qi WANG, Hu YANG, Feng HE, Zhifan FENG, Chunguang CHAI, Yong ZHU
  • Publication number: 20230011430
    Abstract: An electronic device includes a memory configured to store instructions, and a processor configured to execute the instructions to configure the processor to obtain a first heat map feature and a first coordinate value feature based on a face image, and detect a face key point based on the first heat map feature and the first coordinate value feature.
    Type: Application
    Filed: July 8, 2022
    Publication date: January 12, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jian ZHAO, Seungju HAN, Feng ZHU, Han XU, Jingjing HAN, Min YANG
  • Patent number: 11550935
    Abstract: Provided is a method for blockchain-based recordkeeping and implementable by a terminal device. The method comprises: obtaining target data; computing a data digest of the target data, and extracting a key segment from the target data; signing, in a secure operation environment included in the terminal device, the data digest and/or the key segment based on a private key associated with the terminal device to generate a signature; and submitting to a blockchain the data digest, the key segment, and the signature, for one or more nodes in the blockchain to verify the signature based on a public key corresponding to the private key, and to record the data digest and the key segment in the blockchain in response to the signature being verified to be valid.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: January 10, 2023
    Assignee: ADVANCED NEW TECHNOLOGIES CO., LTD.
    Inventors: Hong Zhang, Haitao Jiang, Linqing Wang, Xinyu Weng, Fuqiang Li, Feng Lin, Jun Wu, Xiaodong Zeng, Lei Yang
  • Patent number: 11551422
    Abstract: Various implementations disclosed herein include devices, systems, and methods that generate floorplans and measurements using a three-dimensional (3D) representation of a physical environment generated based on sensor data.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: January 10, 2023
    Assignee: Apple Inc.
    Inventors: Feng Tang, Afshin Dehghan, Kai Kang, Yang Yang, Yikang Liao, Guangyu Zhao
  • Patent number: 11552103
    Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Bo-Feng Young, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 11551968
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Wen Hsueh, Jiing-Feng Yang, Chii-Ping Chen, Po-Hsiang Huang, Chang-Wen Chen, Cai-Ling Wu
  • Patent number: 11553273
    Abstract: A passive diaphragm assembly includes a counterweight member, a first diaphragm and a second diaphragm. The first diaphragm and the second diaphragm are spaced apart from each other, are connected respectively to opposite ends of the counterweight member, and cooperate with the counterweight member to define an air space thereamong.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: January 10, 2023
    Assignee: Jabil Circuit (Singapore) Pte. Ltd.
    Inventors: Wen Hong Wang, Ching Feng Lin, Chia Chien Chen, Po-Cheng Huang, Shih-Hsien Yang
  • Publication number: 20230005280
    Abstract: A method of recognizing target objects in images obtains a detection image of a target object. A template image is generated according to the target object. The detection image is compared with the template image to obtain a comparison result. Candidate regions of the target object are determined in the detection image according to the comparison result. At least one target region of the target object is obtained from the candidate regions. The method detects target objects in images very rapidly.
    Type: Application
    Filed: May 18, 2022
    Publication date: January 5, 2023
    Inventors: CHENG-FENG WANG, HUI-XIAN YANG, LI-CHE LIN
  • Publication number: 20230002821
    Abstract: The present invention belongs to the fields of biomedical technology and molecular diagnosis. Disclosed is a high-throughput detection method for a rare mutation of a gene, comprising: designing specific probes; connecting Y-shaped universal linkers to a test DNA subjected to fragmentation processing, and performing amplification and enrichment of a target site by universal sequence combination of the specific probes and the linkers; performing genomic sequence alignment on sequences to be sequenced; sorting and analyzing said sequences at the same starting and ending positions, and filtering sequencing errors; and after the data filtering, the sequencing depth count of a reference allele of the target site being a, and the sequencing depth count of other alleles being b, and thus the actual mutation ratio of the site being b/(a+b).
    Type: Application
    Filed: May 28, 2020
    Publication date: January 5, 2023
    Inventors: Weishi YU, Mengmeng LIANG, Feng YANG
  • Publication number: 20230005284
    Abstract: A computer-implemented method is provided. The method includes: obtaining a sample text and a sample image corresponding to the sample text; labeling a true semantic tag for the sample text according to a first preset rule; obtaining a text feature representation of the sample text and a predicted semantic tag output by a text coding sub-model; obtaining an image feature representation of the sample image output by an image coding sub-model; calculating a first loss based on the true semantic tag and the predicted semantic tag; calculating a contrast loss based on the text feature representation of the sample text and the image feature representation of the sample image; adjusting parameters of the text coding sub-model based on the first loss and the contrast loss; and adjusting parameters of the image coding sub-model based on the contrast loss.
    Type: Application
    Filed: September 13, 2022
    Publication date: January 5, 2023
    Inventors: Feng HE, Qi WANG, Hu YANG, Shuai CHEN, Zhifan FENG, Chunguang CHAI
  • Patent number: 11545619
    Abstract: A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsing-Hsiang Wang, Han-Ting Lin, Yu-Feng Yin, Sin-Yi Yang, Chen-Jung Wang, Yin-Hao Wu, Kun-Yi Li, Meng-Chieh Wen, Lin-Ting Lin, Jiann-Horng Lin, An-Shen Chang, Huan-Just Lin