Patents by Inventor Feng Yi

Feng Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20190013321
    Abstract: A method of forming semiconductor memory device includes the following steps. Firstly, a substrate is provided and the substrate includes a cell region. Then, plural bit lines are disposed within the cell region along a first direction, with each of the bit line includes a tri-layered spacer structure disposed at two sides thereof. Next, plural of first plugs are formed within the cell region, with the first plugs being disposed at two sides of each bit lines. Furthermore, plural conductive patterns are formed in alignment with each first plugs. Following theses, a chemical reaction process is performed to modify the material of a middle layer of the tri-layered spacer structure, and a heat treatment process is performed then to remove the modified middle layer, thereto form an air gap layer within the tri-layered spacer structure.
    Type: Application
    Filed: May 28, 2018
    Publication date: January 10, 2019
    Inventors: Yi-Ching Chang, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • SEMICONDUCTOR STRUCTURE HAVING AIR GAP BETWEEN GATE ELECTRODE AND DISTAL END PORTION OF ACTIVE AREA
    Publication number: 20190006368
    Abstract: A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.
    Type: Application
    Filed: July 21, 2017
    Publication date: January 3, 2019
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Semiconductor memory device with bit line contact structure and method of forming the same
    Patent number: 10170362
    Abstract: The present invention provides a method of forming a semiconductor device. First, providing a substrate, and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: January 1, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Yu-Cheng Tung, Fu-Che Lee, Ming-Feng Kuo
  • Method of forming patterned structure
    Patent number: 10170310
    Abstract: A method of forming a patterned structure is provided in the present invention. A hard mask layer is formed on a material layer before a first etching process and a second etching process for forming a first opening and a second opening partially overlapping with each other in the hard mask layer. The hard mask layer having the first opening and the second opening is then used in a third etching process performed to the material layer. A fourth etching process is performed to the hard mask layer and a dielectric layer disposed under the material layer after the third etching process. The material of the hard mask layer is identical to the material of the dielectric layer, and the fourth etching process may be used to remove the hard mask layer and form a trench in the dielectric layer accordingly.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: January 1, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan
  • METHOD OF FORMING SEMICONDUCTOR DEVICE
    Publication number: 20180374702
    Abstract: A method of forming a semiconductor device includes the following steps. First of all, a material layer is formed on a substrate, and a sidewall image transferring process is performed to form plural first mask patterns on the material layer, with the first mask patterns parallel extended along a first direction. Next, a pattern splitting process is performed to remove a portion of the first mask patterns to form plural second openings, with the second openings parallel extended along a second direction, across the first mask patterns. Then, the material layer is patterned by using rest portions of the first mask patterns as a mask to form plural patterns arranged in an array.
    Type: Application
    Filed: July 27, 2017
    Publication date: December 27, 2018
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Ching Chang
  • Patterning method
    Patent number: 10153165
    Abstract: The present invention pertains to a patterning method. By taking advantage of the etching loading effect due to different pattern densities in the memory cell region and the peripheral region, the first hard mask is not masked when anisotropically etching the first hard mask within the memory cell region.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: December 11, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ming-Feng Kuo, Chien-Cheng Tsai
  • DEBLOCKING FILTER FOR HIGH DYNAMIC RANGE (HDR) VIDEO
    Publication number: 20180352264
    Abstract: Methods of in-loop deblocking filter for high dynamic range (HDR) video compression are disclosed. HDR processing and standard dynamic range (SDR) processing adopt different electro-optical transfer function (EOTF) to convert digital code words to linear luminance. For compressing HDR video, EOTF is proposed to be involved in the selection of two deblocking parameters, ? and tC, which control the strength of deblocking filter. In local activity checking for filter decisions, the calculated local signal characteristics and the thresholds are adjusted according to EOTF. After deblocking filter, the clipping range is modified based on EOTF. The chroma deblocking filter is also extended to inter-inter block boundary.
    Type: Application
    Filed: June 2, 2017
    Publication date: December 6, 2018
    Inventors: Mei Guo, Feng Yi, Jun Xin, Chris Y. Chung, Yeping Su, Xiaosong Zhou, Jun Xu, Hsi-Jung Wu, Jingteng Xue
  • Semiconductor device and method for fabricating the same
    Patent number: 10147726
    Abstract: A method for fabricating a semiconductor device includes the following steps. First, a contact structure is formed in the insulating layer. Preferably, the contact structure includes a bottom portion in part of the insulating layer and a top portion on part of the bottom portion and extending to cover part of the insulating layer. Next, a dielectric layer is formed on the bottom portion and the top portion, part of the dielectric layer is removed to form a first opening exposing part of the top portion and part of the bottom portion, and a capacitor is formed in the first opening and contacting the pad portion and the contact portion directly.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: December 4, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Semiconductor device and method for fabricating the same
    Patent number: 10147728
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first trench in a substrate; forming a first shallow trench isolation (STI) in the first trench; forming a first patterned mask on the substrate; and using the first patterned mask to remove part of the first STI for forming a second trench and remove part of the substrate for forming a third trench. Preferably, a bottom surface of the third trench is lower than a bottom surface of the second trench.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: December 4, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • SEMICONDUCTOR DEVICE
    Publication number: 20180342425
    Abstract: A semiconductor device includes a first gate structure in a substrate and a second gate structure in the substrate and adjacent to the first gate structure. Preferably, a top surface of the first gate structure and a top surface of the second gate structure are lower than a top surface of the substrate and a number of work function metal layers in the first gate structure and the second gate structure are different.
    Type: Application
    Filed: July 18, 2018
    Publication date: November 29, 2018
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Yu-Cheng Tung, Ming-Feng Kuo, Li-Chiang Chen
  • SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20180342613
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and at least a gate trench extending along a first direction formed in the substrate. A gate dielectric layer is formed conformally covering the gate trench. A gate metal is formed on the gate dielectric layer and filling the gate trench. A plurality of intervening structures are arranged along the first direction in a lower portion of the gate trench and disposed between the gate metal and the gate dielectric layer.
    Type: Application
    Filed: April 1, 2018
    Publication date: November 29, 2018
    Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20180337184
    Abstract: A method for fabricating a semiconductor device includes the following steps. First, a contact structure is formed in the insulating layer. Preferably, the contact structure includes a bottom portion in part of the insulating layer and a top portion on part of the bottom portion and extending to cover part of the insulating layer. Next, a dielectric layer is formed on the bottom portion and the top portion, part of the dielectric layer is removed to form a first opening exposing part of the top portion and part of the bottom portion, and a capacitor is formed in the first opening and contacting the pad portion and the contact portion directly.
    Type: Application
    Filed: June 22, 2017
    Publication date: November 22, 2018
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • METHOD FOR FABRICATING AIR GAP ADJACENT TO TWO SIDES OF BIT LINE
    Publication number: 20180337186
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.
    Type: Application
    Filed: July 8, 2018
    Publication date: November 22, 2018
    Inventors: Yi-Ching Chang, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • EMBEDDED SUBSTRATE PACKAGE STRUCTURE
    Publication number: 20180315712
    Abstract: Provided is an embedded substrate package structure, including, from top to bottom, a fourth dielectric layer, a second substrate, a chip with a fifth dielectric layer, a third dielectric layer, a second dielectric layer, a first substrate and a first dielectric layer; wherein the substrates are disposed respectively with wire layers and through holes, and each of dielectric layers is disposed with openings, conductive bumps or conductive pads, wire layers, through holes, and chip to collectively form electrical connection. The chip is electrically connected to the substrate in a flip-chip manner, and the back of the chip interfaces a dielectric layer. Compared to the prior art which chip bonding is in face-up mode, the packaging structure with the face-down chip of the present invention can simplify the manufacturing process by the flip-chip method.
    Type: Application
    Filed: November 20, 2017
    Publication date: November 1, 2018
    Inventors: Sung-Lien He, Chun-Yuan Hou, Tung-Chuan Wang, Hsi-Ying Yuan, Feng-Yi Chang
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20180315759
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.
    Type: Application
    Filed: March 14, 2018
    Publication date: November 1, 2018
    Inventors: Chia-Liang Liao, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Wang Zhan
  • Embedded substrate package structure
    Patent number: 10115673
    Abstract: Provided is an embedded substrate package structure, including, from top to bottom, a fourth dielectric layer, a second substrate, a chip with a fifth dielectric layer, a third dielectric layer, a second dielectric layer, a first substrate and a first dielectric layer; wherein the substrates are disposed respectively with wire layers and through holes, and each of dielectric layers is disposed with openings, conductive bumps or conductive pads, wire layers, through holes, and chip to collectively form electrical connection. The chip is electrically connected to the substrate in a flip-chip manner, and the back of the chip interfaces a dielectric layer. Compared to the prior art which chip bonding is in face-up mode, the packaging structure with the face-down chip of the present invention can simplify the manufacturing process by the flip-chip method.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: October 30, 2018
    Inventors: Sung-Lien He, Chun-Yuan Hou, Tung-Chuan Wang, Hsi-Ying Yuan, Feng-Yi Chang
  • ULTRASOUND STIMULATION HELMET
    Publication number: 20180304101
    Abstract: An ultrasound stimulation helmet (100) configured to regulate an endogenous neurotrophic factor in a brain or expression of proteins related to a neurodegenerative disease comprises: a main body (1) having a forehead perimeter adjustment knob (12), a back head perimeter adjustment knob (13), a fastening support frame (14), and multiple position adjustment knobs (15); and multiple ultrasound probes (2) detachably mounted on the main body (1), wherein the ultrasound probe (2) has a frequency adjustment button and an intensity adjustment button to respectively control an output frequency and output intensity of the ultrasound probe (2), and other ultrasound parameters and an angle of the ultrasound probe (2) itself are adjustable as well.
    Type: Application
    Filed: October 15, 2015
    Publication date: October 25, 2018
    Inventor: Feng-Yi Yang
  • Method of fabricating semiconductor device
    Patent number: 10103250
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Wei-Hao Huang
  • Manufacturing method for forming a semiconductor structure
    Patent number: 10103019
    Abstract: The present invention provides a method of fabricating a semiconductor structure. Firstly, a substrate is provided, a dense region and an isolation region are defined, next, a first dielectric layer is formed on the dense region and the isolation region, and then a plurality of first recesses are formed in the first dielectric layer within the dense region, and a second recess is formed in the first dielectric layer within the isolation region, wherein the width of the second recess is greater than three times of the width of each first recess. Afterwards, a second dielectric layer is then filled in each first recess and the second recess, wherein a top surface of the second dielectric layer within the isolation region is higher than a top surface of the second dielectric layer within the dense region. Next, an etching back process is performed, to remove the second dielectric layer.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: October 16, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • SUPERABSORBENT POLYMER AND THE METHOD OF FABRICATING THE SAME
    Publication number: 20180282515
    Abstract: A superabsorbent polymer includes polymeric particles, surface cross-linking agents and an extract of a plant of Sapindaceae. The polymeric particles have cross-linking inside the polymeric particles. The surface cross-linking agents are covalently bound to the surface of the polymeric particles so as to constitute a layer of surface cross-linked region at the surface of each polymeric particle, and the extract of the plant of Sapindaceae covers the surface of the polymeric particles.
    Type: Application
    Filed: November 23, 2017
    Publication date: October 4, 2018
    Inventors: Zhong-Yi Chen, Yu-Yen Chuang, Li-Han Huang, Yu-Sam Lin, Feng-Yi Chen, Ching-Hua Liang