Patents by Inventor Feng Yi

Feng Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patterning method
    Patent number: 10460939
    Abstract: A patterning method includes the following steps. A second mask layer is formed on a first mask layer. A patterning process is performed to the first mask layer and the second mask layer. The first mask layer is patterned to be a first mask pattern, and the second mask layer is patterned to be a second mask pattern formed on the first mask pattern. A first trim process is performed to the second mask pattern. A width of the second mask pattern is smaller than a width of the first mask pattern after the first trim process. A cover layer is formed covering the first mask pattern and the second mask pattern after the first trim process, and an etching process is performed to the first mask pattern after the step of forming the cover layer.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: October 29, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Hsin-Yu Chiang
  • PATTERNING METHOD
    Publication number: 20190318930
    Abstract: A patterning method includes the following steps. A second mask layer is formed on a first mask layer. A patterning process is performed to the first mask layer and the second mask layer. The first mask layer is patterned to be a first mask pattern, and the second mask layer is patterned to be a second mask pattern formed on the first mask pattern. A first trim process is performed to the second mask pattern. A width of the second mask pattern is smaller than a width of the first mask pattern after the first trim process. A cover layer is formed covering the first mask pattern and the second mask pattern after the first trim process, and an etching process is performed to the first mask pattern after the step of forming the cover layer.
    Type: Application
    Filed: May 9, 2018
    Publication date: October 17, 2019
    Inventors: Feng-Yi Chang, Fu-Che Lee, Hsin-Yu Chiang
  • Semiconductor memory device and method of forming the same
    Patent number: 10446554
    Abstract: A semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: October 15, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • METHOD OF FORMING SEMICONDUCTOR STRUCTURE
    Publication number: 20190311901
    Abstract: The present invention provides a method of forming a semiconductor structure including the following steps. Firstly, a target layer is formed on a substrate, and a plurality of mandrels is formed on the target layer. Next, a material layer is formed on the target layer to cover the mandrels. Then, an etching process is performed to partially remove each of the mandrel and the material layer covered on each mandrel, to form a plurality of mask. Finally, the target layer is patterned through the masks, to form a plurality of patterns. Through the present invention, each mask comprises an unetched portion of each mandrel and a spacer portion of the material covered on each mandrel, and a dimension of each of the patterns is larger than a dimension of each of the mandrel.
    Type: Application
    Filed: May 3, 2018
    Publication date: October 10, 2019
    Inventors: Gang-Yi Lin, Feng-Yi Chang, Ying-Chih Lin, Fu-Che Lee
  • Electronic apparatus having touch pad and operating method of electronic apparatus
    Patent number: 10437468
    Abstract: An electronic apparatus and an operating method of the electronic apparatus are provided. The electronic apparatus includes a display unit, a base, a touch pad and a processing unit. The base is coupled to the display unit. The touch pad is disposed on the base, includes touch areas and receives a touch action performed by the user on any touch area. The processing unit is coupled to the touch pad and sets a display frame of the display unit into display areas according to a position of each touch area, so that each touch area has the corresponding display area at a corresponding position on the display unit. After the touch pad received a first touch event, the processing unit obtains a first touch area where the first touch event is generated, and displays a first user interface in a first display area corresponding to the first touch area.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: October 8, 2019
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Feng-Yi Yu, Chia-Shin Weng, Hsin-Pei Tsai, Jih-Houng Lee, Kuan-Yu Chen
  • Method of fabricating contact hole
    Patent number: 10438842
    Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: October 8, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Ingtegrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20190304909
    Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
    Type: Application
    Filed: June 19, 2019
    Publication date: October 3, 2019
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang
  • METHOD FOR FORMING HARD MASK
    Publication number: 20190304777
    Abstract: The present invention provides a method for fabricating a hard mask, comprising: firstly, a first material layer and a second material layer are provided on the first material layer, a cell region and a peripheral region are defined thereon, and then a plurality of sacrificial patterns and a plurality of spacers are formed in the cell region on the second material layer, each two spacers are located at two sides of each of the sacrificial patterns. Afterwards, a first etching step is performed to remove the sacrificial patterns, a second etching step is performed to remove a portion of the second material layer and expose a portion of the first material layer within the cell region, and a third etching step is performed to remove portions of the first material layer, so as to forma plurality of first recesses in the first material layer.
    Type: Application
    Filed: April 26, 2018
    Publication date: October 3, 2019
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin
  • CAPACITOR STRUCTURE AND FABRICATION METHOD THEREOF
    Publication number: 20190304981
    Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Semiconductor device and method for forming the same
    Patent number: 10431679
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and at least a gate trench extending along a first direction formed in the substrate. A gate dielectric layer is formed conformally covering the gate trench. A gate metal is formed on the gate dielectric layer and filling the gate trench. A plurality of intervening structures are arranged along the first direction in a lower portion of the gate trench and disposed between the gate metal and the gate dielectric layer.
    Type: Grant
    Filed: April 1, 2018
    Date of Patent: October 1, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee
  • SEMICONDUCTOR STRUCTURE HAVING AIR GAP BETWEEN GATE ELECTRODE AND DISTAL END PORTION OF ACTIVE AREA AND FABRICATION METHOD THEREOF
    Publication number: 20190296020
    Abstract: A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.
    Type: Application
    Filed: May 15, 2019
    Publication date: September 26, 2019
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • PATTERNING METHOD AND PATTERNED STRUCTURE
    Publication number: 20190295840
    Abstract: A patterning method includes the following steps. A mask layer is formed on a material layer. A first hole is formed in the mask layer by a first photolithography process. A first mask pattern is formed in the first hole. A second hole is formed in the mask layer by a second photolithography process. A first spacer is formed on an inner wall of the second hole. A second mask pattern is formed in the second hole after the step of forming the first spacer. The first spacer surrounds the second mask pattern in the second hole. The mask layer and the first spacer are removed. The pattern of the first mask pattern and the second mask pattern are transferred to the material layer by an etching process.
    Type: Application
    Filed: April 18, 2018
    Publication date: September 26, 2019
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Method for fabricating air gap adjacent to two sides of bit line
    Patent number: 10418367
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.
    Type: Grant
    Filed: July 8, 2018
    Date of Patent: September 17, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Ching Chang, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • BURIED WORD LINE OF A DYNAMIC RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME
    Publication number: 20190267385
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 29, 2019
    Inventors: Feng-Yi Chang, Chun-Hsien Lin, Fu-Che Lee
  • Contact hole structure and fabricating method of contact hole and fuse hole
    Patent number: 10396048
    Abstract: A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 27, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chin-Hsin Chiu
  • Postpartum cells derived from placental tissue, and methods of making and using the same
    Patent number: 10383898
    Abstract: Cells derived from postpartum placenta and methods for their isolation are provided by the invention. The invention further provides cultures and compositions of the placenta-derived cells. The placenta-derived cells of the invention have a plethora of uses, including but not limited to research, diagnostic, and therapeutic applications.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 20, 2019
    Assignee: Depuy Synthes Products, Inc.
    Inventors: Anthony J. Kihm, Ian Ross Harris, Sanjay Mistry, Alexander M. Harmon, Darin J. Messina, Agnieszka Seyda, Chin-Feng Yi, Anna Gosiewska
  • Method of forming semiconductor device
    Patent number: 10381239
    Abstract: A method of forming a semiconductor device includes following steps. First of all, a substrate is provided, and a stacked structure is formed on the substrate. Then, a patterned silicon-containing mask layer is formed on the stacked structure, and the stacked structure is partially removed through the patterned silicon-containing mask layer, to form plural openings in the stacked structure. Following these, a bromine covering process is performed, to form a bromide layer on a portion of the patterned silicon-containing mask layer, and a bromide sublimation process is then performed, to completely remove the bromide layer.
    Type: Grant
    Filed: August 19, 2018
    Date of Patent: August 13, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Semiconductor memory device and a manufacturing method thereof
    Patent number: 10381306
    Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 13, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang
  • Capacitor structure and fabrication method thereof
    Patent number: 10373957
    Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 6, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Method of forming semiconductor device
    Patent number: 10366889
    Abstract: A method of forming a semiconductor device includes the following steps. First of all, a material layer is formed on a substrate, and a sidewall image transferring process is performed to form plural first mask patterns on the material layer, with the first mask patterns parallel extended along a first direction. Next, a pattern splitting process is performed to remove a portion of the first mask patterns to form plural second openings, with the second openings parallel extended along a second direction, across the first mask patterns. Then, the material layer is patterned by using rest portions of the first mask patterns as a mask to form plural patterns arranged in an array.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Ching Chang