Abstract: A building photovoltaic data interpolation method based on WGAN and whale optimization algorithm is provided, which includes: obtaining historical building roof photovoltaic output data, perform preprocessing on the historical building roof photovoltaic output data, and uses CNN to build a GAN; describing missing value position of preprocessed data by using a binary mask matrix, and setting Wasserstein distance to define a loss function of a GAN generator and a discriminator; taking the loss function as a fitness function, optimizing an input to the GAN generator through a whale optimization algorithm and obtaining optimized candidate samples; fusing the optimized candidate samples and a photovoltaic data processed by the binary mask matrix to obtain completed reconstructed samples, so as to improve the complementary accuracy, optimize the random noise, remove the unfavorable influencing components, and provide services for building rooftop PV data interpolation more accurately.

Abstract: The technology of this application relates to a frontlight module and a display apparatus. The frontlight module is disposed on a side of a display panel. The frontlight module includes a light source, a light guide plate, and light guide dots. The light guide plate includes a first surface and a second surface that are disposed opposite to each other. The display panel is disposed facing the second surface. The light source is disposed on a side surface of the light guide plate. A plurality of light guide dots are disposed on the first surface or the second surface of the light guide plate. Each light guide dot has a light guide surface disposed at an angle with respect to a surface of the light guide plate. Light is fully reflected and/or refracted on the light guide surfaces to propagate to the display panel.

Abstract: A material conveying device includes a base frame, a first conveying unit, a second conveying unit and a transfer assembly. The first conveying unit is provided on the base frame, the second conveying unit is provided on the base frame, and the transfer assembly is provided on the base frame and can transfer a material between the first conveying unit and the second conveying unit. The present disclosure further provides a processing equipment facilitating material distribution and a material distribution method.

Abstract: A user input in a source language is received. A set of contextual data is received. The user input is encoded into a user input feature vector. The set of contextual data is encoded into a context feature vector. The user input feature vector and the context feature vector are used to generate a fusion vector. An adaptive neural network is trained to identify a second context feature vector, based on the fusion vector. A second user input in the source language is received for translation into a target language. The adaptive neural network is used to determine, based on the second context feature vector, a second user input feature vector. The second user input feature vector is decoded, based on the source language and the target language, into a target language output. A user is notified of the target language output.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

Abstract: The present disclosures discloses a precooler-based transcritical CO2 heat pump system and a control method of a waterway two-way valve thereof, in which a transcritical CO2 heat pump system is assisted by a precooler system. A circulating waterway is divided into two parts in the system through a three-way diversion valve and a three-way confluence valve and is connected to a waterway bypass valve through a waterway two-way regulating valve. An ambient temperature sensor, an evaporation fin temperature sensor and an evaporation pressure sensor are provided, and a programmable logic controller is used as a core for acquisition, operation and control.

Abstract: The present invention provides a preparation method of a battery composite material, wherein a precursor with the chemical formula FePO4 is formed by introducing air or oxygen during calcination. The precursor is then reacted with a first reactant containing lithium atoms and a carbon source to form a battery composite material with the chemical formula LiFePO4.

Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

Abstract: The present disclosure provides a semiconductor structure, including a first metal line over a first region of the substrate, a first magnetic tunnel junction (MTJ) and a second MTJ over the first region of the substrate, and a top electrode extending over the first MTJ and the second MTJ, wherein the top electrode includes a protruding portion at a bottom surface of the top electrode.

Abstract: A memory array device includes an array of memory cells located over a substrate, a memory-level dielectric layer laterally surrounding the array of memory cells, and top-interconnection metal lines laterally extending along a horizontal direction and contacting a respective row of top electrodes within the memory cells. Top electrodes of the memory cells are planarized to provide top surfaces that are coplanar with the top surface of the memory-level dielectric layer. The top-interconnection metal lines do not extend below the horizontal plane including the top surface of the memory-level dielectric layer, and prevent electrical shorts between the top-interconnection metal lines and components of memory cells.

Abstract: The present invention provides a new architecture of system-on-chip ultrasonic transducer array. It is based on fusion bond of two active wafers which have prefabricated CMOS integrated circuits and CMUT structures; precise thin-down of one wafer to form CMUT monocrystalline silicon membrane; and then to vertically connect CMUT array to CMOS IC layers underneath. This architecture can realize a high-density CMUT array with multiple layers of CMOS devices, such as all supporting CMOS ICs, to achieve a SOC solution. The present invention further provides a manufacturing method for above-mentioned SOC CMUT approach, and this manufacturing process can be realized in both 8 inch and 12-inch wafer manufacturing fabs. The disclosed manufacturing processes are more compatible with existing CMOS process flow, more cost-competitive for mass production.

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

Abstract: A memory array device includes an array of memory cells located over a substrate, a memory-level dielectric layer laterally surrounding the array of memory cells, and top-interconnection metal lines laterally extending along a horizontal direction and contacting a respective row of top electrodes within the memory cells. Top electrodes of the memory cells are planarized to provide top surfaces that are coplanar with the top surface of the memory-level dielectric layer. The top-interconnection metal lines do not extend below the horizontal plane including the top surface of the memory-level dielectric layer, and prevent electrical shorts between the top-interconnection metal lines and components of memory cells.

Abstract: The present disclosure discloses a method for liquid fermentation of black tea juice by using aged green tea and belongs to the technical field of tea leaf processing. The method comprises the following process steps: mixing aged green tea with hot water for a water bath-assisted extraction; adding a tannase into a crude catechin extract for a water bath-assisted enzymolysis; freeze-withering fresh tea leaves; homogenizing the freeze-withered leaves; pouring a homogenate into a primarily enzymolyzed crude catechin extract, adding a ?-glucosidase for secondary enzymolysis and performing fermentation; and treating a fermentation broth by microwave, and performing filtration and cooling to a room temperature.

Abstract: An artificial valve and a valve delivery system are provided. The artificial valve includes a top stent, a middle stent and a bottom stent. The top stent, the middle stent and the bottom stent are connected in sequence; the top stent is circumferentially provided with at least three locking stents; each locking stent has a locking end at the top; the middle stent is provided with at least three valve leaflet fixing parts; in the unlocked state of each locking end, the diameter of the circumference where the uppermost edges of the three valve leaflet fixing parts are located is ?1, and in the locked state of each locking end, the diameter of the circumference where the uppermost edges of the three valve leaflet fixing parts are located is ?2, which is larger than or equal to 74% of ?1.

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

Abstract: The present disclosure relates integrated chip structure. The integrated chip structure includes a memory array having a plurality of memory devices arranged in a plurality of rows and a plurality of columns. A word-line is coupled to a first set of the plurality of memory devices disposed within a first row of the plurality of rows. A bit-line is coupled to a second set of the plurality of memory devices disposed within a first column of the plurality of columns. A local interconnect extends in parallel to the bit-line and is coupled to the bit-line and two or more of the second set of the plurality of memory devices. The local interconnect is coupled to the bit-line by a plurality of interconnect vias that are between the local interconnect and the bit-line.

Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a first spacer. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode, and at least one of the first and second source/drain regions includes a first portion and a second portion between the first portion and the gate electrode. The first spacer is disposed on the channel layer. The first spacer is disposed on a first sidewall of the second portion of the at least one of the first and second source/drain regions, and the first portion is disposed on the first spacer.

Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.