Abstract: An automatic target image acquisition and calibration system for application in a defect inspection system is disclosed. During the defect inspection system working normally, the automatic target image acquisition and calibration system is configured to find a recognition structure from an article under inspection, and then determines a relative position and a relative 3D coordinate if the article. Therefore, a robotic arm is controlled to carry a camera to precisely face each of a plurality of inspected surfaces of the article, such that a plurality of article images are acquired by the camera. It is worth explaining that, during the defect inspection of the article, there is no need to modulate an image acquiring height and an image acquiring angle of the camera and an illumination of a light source.

Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.

Abstract: A hand-held scanning probe is included in an optical scanning system. The hand-held scanning probe includes a housing and an optical component. The optical component includes a first lens, a reflector, a two-dimensional beam scanning mechanism, a splitter and a second lens. The first lens is used to receive a laser beam split by a fiber-coupled splitter and convert the laser beam into a form of collimated light. The reflector is used to refract the laser beam. The two-dimensional beam scanning mechanism provides the laser beam to a surface for two-dimensional scanning, producing a swing beam. The splitter is used to separate a scanning end beam returned from the test specimen from an illumination beam into two different light paths. The second lens is used to focus the swing beam at the test surface to form the scanning end beam for scanning. An optical scanning system is also provided.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: Semiconductor device structure and methods of forming the same are described. The structure includes a dielectric layer disposed over an epitaxy source/drain region and a conductive feature disposed in the dielectric layer. The conductive feature includes a metal liner including a first material and a metal fill surrounded by the metal liner. The metal fill includes the first material having a first grain size. The conductive feature further includes a metal cap disposed on the metal liner and the metal fill, and the metal cap includes the first material having a second grain size different from the first grain size.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.

Abstract: A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A parallel optical scanning inspection device, comprising a light source unit, an interference unit, a beam splitting unit, an optical path adjustment unit, a plurality of scanning units and a receiving unit. The light source unit provides initial light to an interference unit. The interference unit divides the initial light into reference light and sampling light. The beam splitting unit splits the sampling light into a plurality of sampling light beams. The optical path adjustment unit adjusts the plurality of sampling light beams into scanning light beams with different optical paths. Each of the scanning units receives one of the scanning light beams. A sample is scanned by the scanning light beams such that each of the scanning units receives detection light reflected or scattered from different positions of the sample. The receiving unit receives and coheres the reference light and the detection light, respectively, to generate optical information.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.

Abstract: An electronic bolt using wireless communication is disclosed and includes a bolt coil formed on a surface of the bolt circuit board, and configured to receive a wireless energy from an electronic seal; and a chip electrically connected to the bolt coil, and configure to generate a wireless signal containing a unique identification to the bolt coil when the chip is driven by the wireless energy; a holder configured to fix and support the bolt circuit board; and a bolt housing configured to contain the bolt circuit board and the holder; wherein the electronic bolt is locked or unlocked with the electronic seal when the unique identification is confirmed by the electronic seal.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.

Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, the gate electrode including at least a first metal; a conductive layer formed above the gate electrode, the conductive layer including an alloy layer, the alloy layer including at least the first metal and a second metal different from the first metal, the alloy layer extending from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure; and a contact feature disposed above the metal gate structure, wherein the contact feature is in direct contact with a top surface of the conductive layer.