Patents by Inventor Feng-Yu Chang
Feng-Yu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240379378Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. The conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. The gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. Laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao, Chia-Yang Hung, Chia-Sheng Chang, Shu-Huei Suen, Jyu-Horng Shieh, Sheng-Liang Pan, Jack Kuo-Ping Kuo, Shao-Jyun Wu
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Patent number: 12142565Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.Type: GrantFiled: July 27, 2022Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
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Publication number: 20240355740Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.Type: ApplicationFiled: June 30, 2023Publication date: October 24, 2024Inventors: Feng-Yu Chang, Sheng-Hsuan Lin, Shu-Lan Chang, Kai-Yi Chu, Meng-Hsien Lin, Pei-Hsuan Lee, Pei Shan Chang, Chih-Chien Chi, Chun-I Tsai, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai, Syun-Ming Jang, Wei-Jen Lo
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Publication number: 20240355730Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.Type: ApplicationFiled: July 2, 2024Publication date: October 24, 2024Inventors: Jia-En Lee, Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang
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Patent number: 12057392Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.Type: GrantFiled: January 17, 2022Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-En Lee, Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang
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Publication number: 20240250139Abstract: A semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. A topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. The semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. The semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.Type: ApplicationFiled: February 12, 2024Publication date: July 25, 2024Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
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Patent number: 11901426Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.Type: GrantFiled: December 16, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
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Publication number: 20240027331Abstract: A hand-held scanning probe is included in an optical scanning system. The hand-held scanning probe includes a housing and an optical component. The optical component includes a first lens, a reflector, a two-dimensional beam scanning mechanism, a splitter and a second lens. The first lens is used to receive a laser beam split by a fiber-coupled splitter and convert the laser beam into a form of collimated light. The reflector is used to refract the laser beam. The two-dimensional beam scanning mechanism provides the laser beam to a surface for two-dimensional scanning, producing a swing beam. The splitter is used to separate a scanning end beam returned from the test specimen from an illumination beam into two different light paths. The second lens is used to focus the swing beam at the test surface to form the scanning end beam for scanning. An optical scanning system is also provided.Type: ApplicationFiled: September 7, 2022Publication date: January 25, 2024Inventors: MENG-TSAN TSAI, FENG-YU CHANG, BO-HUEI HUANG
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Patent number: 11855154Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.Type: GrantFiled: August 3, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
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Publication number: 20230378325Abstract: Semiconductor device structure and methods of forming the same are described. The structure includes a dielectric layer disposed over an epitaxy source/drain region and a conductive feature disposed in the dielectric layer. The conductive feature includes a metal liner including a first material and a metal fill surrounded by the metal liner. The metal fill includes the first material having a first grain size. The conductive feature further includes a metal cap disposed on the metal liner and the metal fill, and the metal cap includes the first material having a second grain size different from the first grain size.Type: ApplicationFiled: May 23, 2022Publication date: November 23, 2023Inventors: Sheng-Hsuan LIN, Feng-Yu CHANG, Shu-Lan CHANG, I Lee, Chun-Yen LIAO
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Publication number: 20230343712Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.Type: ApplicationFiled: June 30, 2023Publication date: October 26, 2023Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
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Publication number: 20230121981Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.Type: ApplicationFiled: December 16, 2022Publication date: April 20, 2023Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
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Patent number: 11532561Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.Type: GrantFiled: August 4, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
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Patent number: 11532717Abstract: A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.Type: GrantFiled: February 15, 2021Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
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Publication number: 20220359399Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.Type: ApplicationFiled: July 27, 2022Publication date: November 10, 2022Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
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Publication number: 20220341724Abstract: A parallel optical scanning inspection device, comprising a light source unit, an interference unit, a beam splitting unit, an optical path adjustment unit, a plurality of scanning units and a receiving unit. The light source unit provides initial light to an interference unit. The interference unit divides the initial light into reference light and sampling light. The beam splitting unit splits the sampling light into a plurality of sampling light beams. The optical path adjustment unit adjusts the plurality of sampling light beams into scanning light beams with different optical paths. Each of the scanning units receives one of the scanning light beams. A sample is scanned by the scanning light beams such that each of the scanning units receives detection light reflected or scattered from different positions of the sample. The receiving unit receives and coheres the reference light and the detection light, respectively, to generate optical information.Type: ApplicationFiled: November 8, 2021Publication date: October 27, 2022Inventors: WEN-JU CHEN, FENG-YU CHANG, YI-TING LIN
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Publication number: 20220139828Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.Type: ApplicationFiled: January 17, 2022Publication date: May 5, 2022Inventors: Jia-En Lee, Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang
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Patent number: 11227830Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.Type: GrantFiled: August 5, 2019Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-En Lee, Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang
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Publication number: 20210367043Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.Type: ApplicationFiled: August 3, 2021Publication date: November 25, 2021Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
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Patent number: 11107896Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.Type: GrantFiled: May 10, 2019Date of Patent: August 31, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao