Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.

Abstract: An electronic bolt using wireless communication is disclosed and includes a bolt coil formed on a surface of the bolt circuit board, and configured to receive a wireless energy from an electronic seal; and a chip electrically connected to the bolt coil, and configure to generate a wireless signal containing a unique identification to the bolt coil when the chip is driven by the wireless energy; a holder configured to fix and support the bolt circuit board; and a bolt housing configured to contain the bolt circuit board and the holder; wherein the electronic bolt is locked or unlocked with the electronic seal when the unique identification is confirmed by the electronic seal.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.

Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, the gate electrode including at least a first metal; a conductive layer formed above the gate electrode, the conductive layer including an alloy layer, the alloy layer including at least the first metal and a second metal different from the first metal, the alloy layer extending from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure; and a contact feature disposed above the metal gate structure, wherein the contact feature is in direct contact with a top surface of the conductive layer.

Abstract: A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.

Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.

Abstract: A grinding stroke control device for a valve stem grinding apparatus is fixed to a processing machine and provided for gripping a valve stem or a test bar. Using the hand wheel, the dial gauge and the positioning seat can obtain an initial position, then moving the measuring meter of the positioning mechanism along the transverse direction to make sure the valve stem has the right length with a standard valve clearance. By such arrangements, the grinding stroke control device for a stem valve grinding apparatus of the invention can have a less complicated structure and therefore is more convenient to operate.

Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.

Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.

Abstract: A clamping device for an engine parts grinder, and its three-point clamping structure and pivoting control structure. With the three-point clamping structure and the pivoting control structure, the clamping device is capable of clamping the workpiece in a three point clamping manner with a stable clamping force. The pivoting control structure moves in pivoting motion to control the operating member to make the clamping member move downward or upward to clamp or to release the workpiece, and therefore the operation is very simple. Meanwhile, the operating member and the pressing unit provide a one-way self-locking function, and the elastic abutting unit presses against the cam portion of the pressing unit to create a position restricting effect. In addition to providing a stable clamping force, the operating member can be automatically locked when pivoted to a positioning position, which makes the clamping device very convenient to use.

Abstract: A grinding stroke control device for a valve stem grinding apparatus is fixed to a processing machine and provided for gripping a valve stem or a test bar. Using the hand wheel, the dial gauge and the positioning seat can obtain an initial position, then moving the measuring meter of the positioning mechanism along the transverse direction to make sure the valve stem has the right length with a standard valve clearance. By such arrangements, the grinding stroke control device for a stem valve grinding apparatus of the invention can have a less complicated structure and therefore is more convenient to operate.

Abstract: A device of detecting a door/window status includes a signal generating unit and a signal sensing module. The signal generating unit is disposed beside a door/window to generate a position signal. The signal sensing module is disposed opposite the signal generating unit and includes a three-axis accelerometer, a three-axis magnetic force gauge and a microcontroller. The microcontroller reads the position signal generated from the signal generating unit and detection signals generated from the three-axis accelerometer and the three-axis magnetic force gauge while the door/window is operating to thereby determine the position and status of the door/window, thereby enhancing home safety. A method of detecting the door/window status with the device is further introduced.

Abstract: A computer apparatus includes a first cover, a second cover, a motherboard, an expansion device and a detach assisting assembly. The second cover is detachably disposed on the first cove, and has an accommodation space and an opening. The motherboard is disposed between the first and second covers. The expansion device disposed in the accommodation space and connected to the motherboard is drawable from the accommodation space through the opening. The detach assisting assembly disposed in the accommodation space includes a slidable member and a rotatable member. The slidable member is slidable relative to the second cover for rotating the rotatable member to drive the first pressing part to press a side of the expansion device away from the opening, and thereby at least a part of the expansion device protrudes from the accommodation space through the opening.