Patents by Inventor Feng-Yu Hsu

Feng-Yu Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140137469
    Abstract: A tube structure for preserving a flower includes a body having an assembling portion and a storage portion. The assembling portion is defined at a top end of the body. The storage portion is defined at a bottom end of the body. A water chamber is defined in the body. The water chamber communicates with the assembling portion and the storage portion. A surrounding wall is deformable and is formed onto the assembling portion. A through hole is opened on the surrounding wall and communicates with the water chamber. A soft wall is defined around a bottom of the storage portion. A rigid wall is defined around a top of the storage portion. An angle is defined between an inner surface of the surrounding wall and a further inner surface of the rigid wall. The angle is larger than 95 degree.
    Type: Application
    Filed: November 22, 2012
    Publication date: May 22, 2014
    Inventors: Jui-Cheng Lin, Feng-Yu Hsu
  • Patent number: 8084357
    Abstract: A method for manufacturing a multi cap layer includes providing a substrate, forming a multi cap layer comprising a first cap layer and a second cap layer formed thereon on the substrate, forming a patterned metal hard mask layer on the multi cap layer, and performing an etching process to etch the multi cap layer through the patterned hard mask layer and to form an opening in the second cap layer.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: December 27, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Chih Chen, Su-Jen Sung, Feng-Yu Hsu, Chun-Chieh Huang, Mei-Ling Chen, Jiann-Jen Chiou
  • Publication number: 20090283310
    Abstract: A method of manufacturing a cap layer includes providing a substrate having at least a conductive layer, a base layer and a dielectric layer; forming a tensile stress cap layer on the substrate; forming a patterned hard mask layer o the tensile stress cap layer; and performing an etching process to each the tensile stress cap layer through the patterned metal hard mask layer to form at least an opening in the tensile stress cap layer.
    Type: Application
    Filed: July 23, 2009
    Publication date: November 19, 2009
    Inventors: Wei-Chih Chen, Feng-Yu Hsu
  • Publication number: 20090146311
    Abstract: An interconnect structure is disposed on a substrate with a conductive part thereon and includes a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a first UV cutting layer at least between the first porous low-k layer and the second porous low-k layer. The damascene structure is electrically connected with the conductive part. The UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.
    Type: Application
    Filed: February 13, 2009
    Publication date: June 11, 2009
    Applicant: United Microelectronics Corp.
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Chun-Chieh Huang, Jei-Ming Chen, Shu-Jen Sung
  • Patent number: 7514347
    Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: April 7, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Chun-Chieh Huang, Jei-Ming Chen, Shu-Jen Sung
  • Patent number: 7439154
    Abstract: A method for fabricating an interconnect structure is described. A substrate with a conductive part thereon is provided, a first porous low-k layer is formed on the substrate, and then a first UV-curing step is conducted. A damascene structure is formed in the first porous low-k layer to electrically connect with the conductive part, and then a first UV-absorption layer is formed on the first porous low-k layer and the damascene structure. A second porous low-k layer is formed on the first UV-absorption layer, and a second UV-curing step is conducted.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: October 21, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Jim-Jey Huang, Jei-Ming Chen
  • Publication number: 20080251931
    Abstract: A method for manufacturing a multi cap layer includes providing a substrate, forming a multi cap layer comprising a first cap layer and a second cap layer formed thereon on the substrate, forming a patterned metal hard mask layer on the multi cap layer, and performing an etching process to etch the multi cap layer through the patterned hard mask layer and to form an opening in the second cap layer.
    Type: Application
    Filed: April 11, 2007
    Publication date: October 16, 2008
    Inventors: Wei-Chih Chen, Su-Jen Sung, Feng-Yu Hsu, Chun-Chieh Huang, Mei-Ling Chen, Jiann-Jen Chiou
  • Publication number: 20070093053
    Abstract: A method for fabricating an interconnect structure is described. A substrate with a conductive part thereon is provided, a first porous low-k layer is formed on the substrate, and then a first UV-curing step is conducted. A damascene structure is formed in the first porous low-k layer to electrically connect with the conductive part, and then a first UV-absorption layer is formed on the first porous low-k layer and the damascene structure. A second porous low-k layer is formed on the first UV-absorption layer, and a second UV-curing step is conducted.
    Type: Application
    Filed: December 1, 2006
    Publication date: April 26, 2007
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Jim-Jey Huang, Jei-Ming Chen
  • Publication number: 20070085208
    Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV-absorption layer at least between the first and the second porous low-k layers.
    Type: Application
    Filed: October 13, 2005
    Publication date: April 19, 2007
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Jim-Jey Huang, Jei-Ming Chen
  • Publication number: 20070085210
    Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.
    Type: Application
    Filed: January 26, 2006
    Publication date: April 19, 2007
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Chun-Chieh Huang, Jei-Ming Chen, Shu-Jen Sung
  • Publication number: 20060199386
    Abstract: An inlaid copper/barrier interconnect includes a semiconductor substrate; a carbon-doped oxide (CDO) dielectric layer disposed over the semiconductor substrate; a damascene recess etched into the CDO dielectric layer; an alpha-phase tantalum (?-Ta) single-layer barrier sputter deposited on sidewall and bottom of the damascene recess; and a conductive layer deposited directly on the alpha-phase tantalum single-layer barrier, wherein the conductive layer fills the damascene recess. According to one preferred embodiment, the alpha-phase tantalum single-layer barrier has a resistivity of about 25 ??-cm.
    Type: Application
    Filed: December 7, 2005
    Publication date: September 7, 2006
    Inventors: Jim-Jey Huang, Chih-Chien Liu, Feng-Yu Hsu
  • Publication number: 20060199367
    Abstract: A manufacturing method of interconnect is provided. A dielectric layer is provided. A metal layer is formed in the dielectric layer. A fluorine-containing barrier layer is formed on the dielectric layer and covers the metal layer. The fluorine-containing barrier layer is formed by using chemical deposition method and introducing fluorine to the film in-situ.
    Type: Application
    Filed: December 7, 2005
    Publication date: September 7, 2006
    Inventors: Jim-Jey Huang, Chih-Chien Liu, Feng-Yu Hsu, Jei-Ming Chen, Kuo-Chih Lai