Abstract: Provided are a measuring method and apparatus for a damaged part of a vehicle includes: acquiring an image to be processed of a vehicle; acquiring the damaged part of the vehicle in the image to be processed according to the image to be processed; acquiring first position information of key points in the image to be processed according to the image to be processed; determining a transformation relation between the image to be processed and a first fitting plane according to the key points included in the image to be processed and the first position information, where the first fitting plane is a fitting plane determined according to the key points included in the image to be processed on the 3D model; acquiring a projection area of the damaged part in the first fitting plane according to the transformation relation; and measuring the projection area to acquire a measuring result.

Abstract: A thermally managed electrical supply unit is provided. The unit contains an energy unit comprising a battery or a battery pack; a casing of a porous thermally conductive framework comprising a phase change material on at least one surface of the energy unit; at least one heat flux rectifier unit on the thermally conductive framework casing; wherein a surface of the heat flux rectifier opposite to the PF/PCM casing is subject to cooling. Also provided is a method for thermal management of an energy unit comprising absorption of heat from the energy unit within a phase change material, transfer of the heat energy from the phase change material through a heat flux rectifier and removal of the heat transferred across the heat flux rectifier. The flow of heat across the heat flux rectifier is irreversible and the heat flux rectifier acts as an on/off switch to control the heat flow.

Abstract: Conjugates are provided containing a graphene quantum dot, a targeting moiety, and an active agent. The conjugates can be used to provide one or more therapeutic, prophylactic, or diagnostic effects to a subject in need thereof. The subject can be a cancer patient and the active agent an anti-cancer agent. The graphene quantum dots can have an average particle size of about 1-20 nm and a monodisperse size distribution. The size distribution can have a span about 1 or less and/or a coefficient of variance of about 0.5 or less. Methods of making the conjugates are provided. The methods can include conjugating the targeting moiety to the GQD using a reactive coupling group. Methods of treating, preventing, and/or diagnosing a disease or disorder in a patient in need thereof by administering the conjugates are provided.

Abstract: A method for fabricating a multi-layer porous wick structure including, providing a first mold set comprising a negative mold and a positive mold, introducing metal particles in the negative mold defining a first porous wick layer, and sintering the metal particles within the negative mold while interfaced with the positive mold to form the first porous wick layer. The method further includes providing a second mold set comprising a negative mold and a positive mold corresponding to the negative mold and assembling the first porous wick layer with the negative mold of the second mold set. The method further includes introducing filler particles into the negative mold of the second mold set to form a sacrificial layer with the first porous wick layer, introducing metal particles in the negative mold of the second mold set with the first porous wick layer and the sacrificial layer and sintering the metal particles, thereby forming the multi-layer porous wick structure.

Abstract: A semiconductor device includes a semiconductor substrate, a first SiGe semiconductor fin on the semiconductor substrate, and a dielectric layer on the semiconductor substrate and side surfaces of the first SiGe semiconductor fin. The first SiGe semiconductor fin has a Ge content that gradually changes from bottom to top. The dielectric layer has an upper surface lower than an upper surface of the first SiGe semiconductor fin.

Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

Abstract: The present disclosure relates to a 2,4-disubstituted pyrimidine derivative and the use thereof as a therapeutically effective cyclin-dependent kinase (CDK) inhibitor. In particular, the present disclosure relates to the use of a new 2,4-disubstituted pyrimidine derivatives shown in formula (I) and a pharmaceutical composition thereof as a selective CDK4/6 inhibitor in preventing or treating diseases related to CDK4/6.

Abstract: A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

Abstract: A method of forming a carbonized composition includes providing an organic composition, forming a protective layer over the organic composition, increasing temperature to carbonize the organic composition and for a period of time to form the carbonized composition, and removing the protective layer from the carbonized composition.

Abstract: A channel latency determining method, a positioning method, and device, the method including obtaining, by a communications device, device location information of a calibration user equipment (UE), calculating a propagation delay according to the device location information and prestored location information of an antenna, where the propagation delay is a time between transmitting a radio signal by the calibration UE and receiving the radio signal by the antenna, calculating a time of arrival according to the radio signal transmitted by the calibration UE to the antenna, where the time of arrival is a time obtained through calculation according to a time of arrival (TOA) estimation algorithm, and determining a channel latency according to the propagation delay and the time of arrival, where the channel latency is positively correlated with the time of arrival and is negatively correlated with the propagation delay.

Abstract: A fan-out structure and its manufacturing method are presented, relating to semiconductor techniques. The fan-out structure includes a welding pad; a welding pad extension member contacting the welding pad; and a fan-out line contacting the welding pad extension member, with an elicitation direction of the fan-out line perpendicular to an extension direction of the welding pad. This fan-out structure allows the fan-out line to be horizontally or vertically elicited from the welding pad, and thus remedies the drawbacks associated with an aslant-elicited fan-out line in conventional fan-out structures.

Abstract: Embodiments provide a positioning method, an assistant site, and a system, to improve positioning accuracy of a mobile terminal. The method according to the embodiments of the present invention includes: generating, by an assistant site, a downlink assisted positioning signal; and sending, by the assistant site, the downlink assisted positioning signal to a mobile terminal. The downlink assisted positioning signal can enable a base station to determine position information of the mobile terminal based on a measurement result obtained by the mobile terminal by measuring the downlink assisted positioning signal.

Abstract: An assembly includes at least one heat emitting device and a continuous conformal cooling structure adhering directly to and conforming with surfaces of at least a portion of the at least one heat emitting device. The cooling structure may include a thermally-conductive, electrically-insulative layer adhering directly to surfaces of the at least one heat generating device to provide an electrically nonconductive, continuous, conformal layer covering all such surfaces. An inner metallization layer may be adhered directly to surfaces of at least a portion of the insulative layer. An outer metallization layer may be adhered directly to surfaces of the inner metallization layer to provide a thermally conductive layer covering such surfaces.

Abstract: A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.

Abstract: A fault detection and positioning system for a cell panel in a large-scale photovoltaic array, includes a first photovoltaic panel fault detection and positioning system, a second photovoltaic panel fault detection and positioning system, and/or a third photovoltaic panel fault detection and positioning system. The detection and positioning system can detect faults of panels in the photovoltaic array in real time, especially accurately positioning a photovoltaic panel in which a fault occurs; the number of sensors can be minimized, so that the detection costs can be reduced; and the system can be easily implemented and mounted in existing power stations.

Abstract: A battery management device includes a detection circuit, a charge control circuit, and a discharge control circuit. The detection circuit is configured to output a first control signal and a second control signal according to a volume of a rechargeable battery. The charge control circuit is electrically coupled to the rechargeable battery and the detection circuit, and configured to open a charge loop of the rechargeable battery according to the first control signal. The discharge control circuit is electrically coupled to the rechargeable battery and the detection circuit, and configured to close a discharge path of the rechargeable battery according to the second control signal.

Abstract: A fabrication method for a semiconductor structure is provided. The method includes: forming a base substrate; forming gate structures on the base substrate where each gate structure includes a first gate portion with first doping ions on the base substrate and a second gate portion on the first gate portion; forming a metal layer on the second gate portions; and forming a metal silicide layer by reacting a portion of the metal layer with each second gate portion through an annealing process. When forming the metal silicide layers, a reaction between the metal layer and the second gate portions has a first reacting rate and a reaction between the metal layer and the first gate portions has a second reacting rate; and the second reacting rate is smaller than the first reacting rate.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a hardmask on a second portion of the dielectric layer while exposing a first portion of the dielectric layer; forming a copolymer on the semiconductor structure; performing an annealing treatment such that the copolymer forms a staggered configuration of a first monomer and a second monomer; removing the first monomer; performing a first etching process on the first portion using the second monomer as a mask to form a first trench extending to the semiconductor substrate; removing the second monomer and the first hardmask; and epitaxially growing a first semiconductor fin in the first trench.