Abstract: CD73 (also known as ecto-5?-nucleotidase) inhibitor compounds are provided, as well as compositions and uses thereof for treating or preventing CD73-associated or related diseases, disorders and conditions, including cancer- and immune-related disorders. CD73 inhibitor compounds include compounds having the structure set forth in Formula I and pharmaceutically acceptable esters or salts thereof.

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

Abstract: An apparatus for image processing includes a processor and a depth camera. The processor obtains a first two-dimensional image and focusing information of the first two-dimensional image, and obtains depth information of a part or all of a content captured in the first two-dimensional image via the depth camera. The processor determines a background area of the first two-dimensional image according to the focusing information. The processor also performs bokeh on the background area of the first two-dimensional image according to the depth information.

Abstract: Embodiments of a Generation Node-B (gNB) and methods of communication are disclosed herein. The gNB may be configured with logical nodes including a gNB central unit (gNB-CU) and a gNB distributed unit (gNB-DU). The gNB-CU 106 may determine a first precoding matrix and a second precoding matrix for a precoding of one or more data streams for transmission on a plurality of antennas coupled to the gNB-DU. The precoding may be in accordance with a split functionality between the gNB-CU and the gNB-DU that includes: precoding by the gNB-CU with the first precoding matrix, and precoding by the gNB-DU with the second precoding matrix.

Abstract: A method of forming a carbonized composition includes providing an organic composition, forming a protective layer over the organic composition, increasing temperature to carbonize the organic composition and for a period of time to form the carbonized composition, and removing the protective layer from the carbonized composition.

Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

Abstract: Flash memory devices and fabrication methods thereof are provided. An exemplary method includes providing discrete bit lines on a semiconductor substrate, a first dielectric layer on top surfaces of the bit lines, and a floating gate structure on the first dielectric layer, trenches being formed between adjacent bit lines and on the semiconductor substrate; forming a sacrificial layer with a top surface above the top surfaces of the bit lines in the trenches; forming a second dielectric layer on top and side surfaces of the floating gate structure and the top surface of the sacrificial layer; forming a control gate structure on the second dielectric layer; removing portions of the second dielectric layer, the floating gate structure and the first dielectric layer to expose a portion of the sacrificial layer; and removing the sacrificial layer from the adjacent bit lines and the semiconductor substrate, thereby forming air gaps.

Abstract: The invention relates to modulators of Embryonic Ectoderm Development (EED) and/or Polycomb Repressive Complex 2 (PRC2) useful in the treatment of disorders and diseases associated with EEC and PRC2, being macrocyclic azolopyridine derivatives and compositions thereof of Formula I or a pharmaceutically acceptable salt, prodrug, solvate, hydrate, enantiomer, isomer, or tautomer thereof, wherein X1, X2, X3, A1, A2, Y, R1, R2, R3, and R4 are as described herein.

Abstract: The present application discloses a processing station and a cleaning system. The cleaning system includes a processing station and a cleaning robot, the processing station for evacuating trash collected in the cleaning robot, and including a body formed with a sealing surface, a base located below the sealing surface and configured for supporting a trash cassette having an opening at a top, a suction mechanism and a filter, and an adjustment member connected the body with the base; the adjustment member urges the base to be vertically adjacent to the sealing surface to clamp the trash cassette between the base and the sealing surface, such that the opening edge of the trash cassette abuts against the sealing surface.

Abstract: The present disclosure provides a method and apparatus for recognizing video fine granularity, a computer device and a storage medium, wherein the method comprises: performing sampling processing for video to be recognized to obtain n frames of images, n being a positive integer larger than one; respectively obtaining a feature graph of each frame of image, and determining a summary feature according to respective feature graphs; determining a fine granularity recognition result of a target in the video according to the summary feature. The solution of the present disclosure may be applied to enhance the accuracy of recognition result.

Abstract: There are provided compounds of Formula I, and pharmaceutically acceptable salts and esters thereof, and pharmaceutical compositions thereof, used for inhibition or modulation of the activity of cyclin dependent kinases (CDK) and/or glycogen synthase kinase-3 (GSK-3), for the treatment of disease states or conditions mediated by cyclin dependent kinases and/or glycogen synthase kinase-3, including cancers.

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

Abstract: A vapor chamber heat spreader includes a condenser arranged at a top end of the vapor chamber heat spreader, an evaporator arranged at an opposite end to the condenser; and multi-level wick structures. The multi-level structures include a first planar wick arranged adjacent to the condenser, a second planar wick arranged adjacent to the evaporator, a plurality of condenser posts for supplying liquid condensed by the condenser, a plurality of evaporator posts for supply the liquid towards the evaporator, and a mesh layer. The mesh layer is arranged between the condenser posts and the evaporator posts and configured to separate the condenser posts from the evaporator posts. The mesh layer includes a plurality of vent holes. The mesh layer is a porous layer having high permeability.

Abstract: A USB cable contains: a holder, a body, and a conductive assembly. The holder includes a protective shell, a connection disc, and a decoration cap. The protective shell has a first accommodation chamber, a fixing sheet, and a protection cap. The body includes a receiving seat, a male plug, a locking member, a fixer, a PCB, a resilient piece, and a covering member. The receiving seat has a second accommodation chamber. The conductive assembly includes a first lid, a second lid, a defining sheet, a PCB plug, and a retractable wire. The retractable wire is connected with the PCB of the body, the PCB plug is accommodated in the cross-cross groove of the covering member, the body is received in the first accommodation chamber of the protective shell of the holder, and the receiving seat is connected with the decoration cap.

Abstract: The present invention provides a method and an apparatus for image processing, applied in image processing field, where the method comprises: obtaining a first two-dimensional image and focusing information of the first two-dimensional image, obtaining depth information of a part or all of a content in the first two-dimensional image, determining a background area of the first two-dimensional image according to the focusing information, performing bokeh on the background area of the first two-dimensional image according to the depth information. The above method can reduce requirements for hardware, operate easily, and perform bokeh on the background quickly when performing bokeh on the background.

Abstract: The present invention relates to the field of isobutylene preparation. Disclosed are a catalyst and preparation method thereof, and method for preparing isobutylene by applying the same; the catalyst has a core-shell structure, the core an amorphous silica-alumina particle and/or an aggregate molding thereof, and the shell aluminum oxide comprising silicon and tin; the weight ratio of aluminum oxide comprising silicon and tin to amorphous silica-alumina is 1:60-1:3; in the aluminum oxide comprising silicon and tin, on basis of the weight of aluminum oxide comprising silicon and tin, the content of silicon is 0.5-2 wt %, and of tin is 0.2-1 wt %. The catalyst of the present invention is used to catalyze a mixture of MTBE and TBA to prepare isobutylene, enabling the MTBE cleavage and TBA dehydration reactions to be conducted simultaneously to generate isobutylene, achieving higher conversion rates of TBA and MTBE, and higher selectivity for generating isobutylene.

Abstract: A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.

Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

Abstract: A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.