Abstract: A method and system for achieving increased efficiency in a quadrature modulated power amplifier (11) are disclosed. In some embodiments, a supply path (36, 40) and a gain path (38, 42) are provided in each of an I-channel and a Q-channel. The supply path (36, 40) produces a variable voltage and the gain path (38, 42) produces a gain control signal. The variable voltage and gain control signal are used by a variable gain power amplifier (44, 46) to modulate a local oscillator signal to produce a modulated radio signal.

Abstract: A transformer filter arrangement (30) for passing signals at a fundamental frequency and suppressing signals at one or more interfering frequencies is disclosed. It comprises a transformer (100) having a first winding (110) and a second winding (120), wherein the first winding (110) has a first end (112a) and a second end (122b) and the second winding (120) has a first end (122a) and a second end (122b). It further comprises one or more capacitors (130a-e).

Abstract: A transformer filter arrangement including a transformer having a first winding and a second winding is provided. Both of the first and the second windings are located between an outer border and an inner border, which is inside the outer border. The transformer filter arrangement further includes at least one reactive sub circuit, each including at least one inductor. The first winding of the transformer is divided into a plurality of winding segments. At least a first one of the at least one reactive sub circuit being connected in series with the winding segments of the first winding between two such winding segments, and having at least one of the at least one inductor located inside said inner border.

Abstract: A clock generator circuit may generate a target clock signal and may include a pattern generator to generate a pre-distorted version of a modulation signal from patterns stored by the pattern generator. An up-converter may up-convert the pre-distorted version of the modulation signal and a radio frequency lock oscillator signal to obtain an RF clock signal having a desired frequency tone. A tone detection circuit may receive the RF clock signal and detect a presence of unwanted tones. A controller may write the patterns corresponding to the pre-distorted version of the modulation signal to the pattern generator based on the detected unwanted tones in the RF clock signal.

Abstract: The invention relates to a complex intermediate frequency (CIF) mixer stage, methods of operation thereof, and methods of calibration thereof. The CIF mixer stage comprises numerous individual mixers driven by IF clock signals to down-convert received IF signals into a set of signals at baseband frequency which are further combined to form a lower side band signal and an upper side band signal. The IF clock signals used have a predefined phase relationship among them, which involves tuneable phase skews. By calibration of the conversion gains and the phases of the IF clock signals the gain and phase imbalance introduced in a preceding radio frequency mixer stage and/or the CIF mixer stage can be cancelled. Further, in-channel IQ leakage control can be applied to the lower side band signal and/or the upper side band signal. The CIF mixer stage can thus effectively suppress image interference and IQ leakage.

Abstract: A digital affine transformation modulator and power amplifier drives a transmitter antenna. The modulator performs an affine transformation on a signal, wherein the I, Q space is mapped to a plurality of sectors. A signal in a sector is expressed as the sum of two vectors, the angles of which define the sector boundaries. A digital power amplifier comprises a plurality of amplifier cells, each cell comprising at least two amplifier units. For a given signal, each amplifier unit selectively amplifies a clock signal having a phase corresponding to one of the boundary angles of the signal's affine transformed sector. A subset of the plurality of amplifier cells receiving each phase clock signal are enabled, based on the magnitude of the associated vector describing the signal in affine transform space. The modulation scheme exhibits higher efficiency than quadrature modulation, without the bandwidth expansion and group delay mismatch of polar modulation.

Abstract: The disclosure relates to a Complex Intermediate Frequency (CIF)-based receiver adapted to process a received signal comprising a signal component at a desired frequency and a signal component as an image frequency. The CIF-based receiver determines the power of the received signal by calibrating the receiver to minimize the power of the signal component at the image frequency that interferes with the signal component at the desired frequency, introduces signal leakage from the image frequency to intentionally degrade the quality of the signal component at the desired frequency, and determines the power of the signal component at the image frequency based on the amount of degradation.

Abstract: A technique for generating a radio frequency signal (302) based on a baseband signal (304) is provided. As to a method aspect of the technique, an amplitude signal (r) and a phase signal (?) depending on the baseband signal (304) are provided. The phase signal is modulated to a carrier frequency. As to another method aspect of the technique, a baseband signal (304) is modified by adding an offset signal to the baseband signal (304). The offset signal prevents the modified baseband signal (316) from entering a first signal region. An amplitude signal (r) and a phase signal (?) is provided based on the modified baseband signal (316). The phase signal (?) is modulated to a carrier frequency (?c). The modulated phase signal (?) is amplified according to the amplitude signal (r) to generate a preliminary radio frequency signal (318).

Abstract: A low noise amplifier comprises at least one amplifying transistor (Ts1; Ts2) configured in a common source configuration to receive an input signal (RFin) at a gate terminal and provide an amplified signal at a drain terminal and at least one feedback path arranged to couple a part of the amplified signal back to the gate terminal and comprising a feedback impedance. The low noise amplifier further comprises a self-coupled step-up transformer having at least one primary winding (Lp) connected to a supply voltage (Vdd) and the drain terminal of the at least one amplifying transistor and at least one self-coupled secondary inductor winding (Lf1; Lf2) arranged in the feedback path. The low noise amplifier provides a better suppression for out-band interference and at the same time it has a wider input match bandwidth, decent conversion gain and decent noise figure without increasing power consumption.

Abstract: A circuit converts a single-ended signal to differential signals that are balanced to have the same amplitudes and opposite phases relative to a reference point of the differential signals. The circuit includes a balance tunable balun, a detector, and a controller. The balance tunable balun has a primary winding, a secondary winding, a control input, and a switched resistor-capacitor (RC) network. The primary winding receives the single-ended signal and the secondary winding outputs the differential signals. The control input receives a control signal and the switched RC network controls the reference point of the differential signals responsive to this control signal. The detector detects the output imbalance and the controller generates the control signal to control the switched RC network to effectively adjust the reference point as needed to reduce that output imbalance. The circuit produces well balanced differential signals over a wide range of signal frequencies.

Abstract: The invention relates to a complex intermediate frequency (CIF) mixer stage, methods of operation thereof, and methods of calibration thereof. The CIF mixer stage comprises numerous individual mixers driven by IF clock signals to down-convert received IF signals into a set of signals at baseband frequency which are further combined to form a lower side band signal and an upper side band signal. The IF clock signals used have a predefined phase relationship among them, which involves tunable phase skews. By calibration of the conversion gains and the phases of the IF clock signals the gain and phase imbalance introduced in a preceding radio frequency mixer stage and/or the CIF mixer stage can be cancelled. Further, in-channel IQ leakage control can be applied to the lower side band signal and/or the upper side band signal. The CIF mixer stage can thus effectively suppress image interference and IQ leakage.

Abstract: A clock generator circuit generates a wanted RF clock signal by using an up-converter, a spurious tone cancellation circuit, a controller, and at least two clock driver/dividers. The spurious tone cancellation circuit includes a tone detection circuit and a tone generation circuit. The up-converter mixes modulation signals with local quadrature RF clock signals to create an up-converted signal having a frequency tone equal to a desired frequency of the wanted RF clock signal. The first clock driver/divider amplifies and clips the up-converted signal into a first-clipped clock signal. The tone detection circuit detects the amplitude and phase of unwanted tones of the first-clipped clock signal in the baseband domain and provides information to the controller, which controls the tone generation circuit to cancel the unwanted tones and create a compensated version of first-clipped clock signal.

Abstract: A complex intermediate frequency mixer (IFM) for frequency translating a received complex intermediate frequency, IF, signal, wherein the received complex IF signal comprises at least two frequency bands located at upper-side and lower-side of 0 Hz, is provided. The complex intermediate frequency mixer comprises a first, second, third and fourth mixer (M1, M2, M3, M4). The complex intermediate frequency mixer further comprises a first, second, third and fourth gain adjusting component (?1, ?2, ?2, ?1), connected to a first, second, third and fourth mixer output (M1-out, M2-out, M3-out, M4-out), respectively. Moreover, a first summing unit (S1), connected to a first gain output (?1-out), a fourth gain output (?1-out) and a third mixer output (M3-out) negated, and second summing unit (S2), connected to the second gain output (?2-out), the third gain output (?2-out) and the fourth mixer output (M4-out), are configured to output a first baseband complex signal of the received complex IF signal.

Abstract: In one or more embodiments taught herein, a multi-band MIMO repeater is configured to translate normal wireless mobile bands into other frequency bands in the physical layer. An advantageous, multi-hop repeater chain includes two or more such repeaters, for propagating downlink signals from a base station, and for propagating uplink signals to the base station. Each such repeater may use paralleled homodyne structure transceivers for better SNR, spectrum combiners for uplink signal aggregation, spectrum separators for downlink signal de-aggregation, water mark signal inserters for optimization, and, among other things, spectrum analyzers for frequency band selection. In at least one such embodiment, a multi-hop repeater chain is configured for MIMO operation in an LTE Advanced or other MIMO network, to deliver high data rate over larger distances—e.g., further away from cell base stations.

Abstract: A circuit converts a single-ended signal to differential signals that are balanced to have the same amplitudes and opposite phases. The circuit includes a balance tunable balun, a detector, and a controller. The balance tunable balun has a primary winding, a secondary winding, a control input, and a switched resistor-capacitor (RC) network. The primary winding receives the single-ended signal and the secondary winding outputs the differential signals. The control input receives a control signal and the switched RC network tunes an output imbalance of the balun responsive to this control signal. The detector detects the output imbalance and the controller generates the control signal to control the switched RC network to reduce that output imbalance. The circuit produces well balanced differential signals over a wide range of signal frequencies, even when asymmetries, process variations, or parasitic capacitance in the balun would otherwise result in imbalance.

Abstract: The second-order inter-modulation distortion, originating in a differential passive mixer core from imbalance between devices, is reduced by compensating for the mismatch or load, by means of tuning the differential output impedance at the mixer core, or the input impedance of a filter coupled to the output of the passive mixer. Compensating for the imbalance allows greater suppression of even-order harmonics in the differential structure, which reduces second-order intermodulation at the output of the mixers. The compensation is achieved by tunable resistive elements that are calibrated by a built-in self-test architecture. The calibration circuit is deactivated during receiver operation.

Abstract: A circuit converts a single-ended signal to differential signals that are balanced to have the same amplitudes and opposite phases. The circuit includes a balance tunable balun, a detector, and a controller. The balance tunable balun has a primary winding, a secondary winding, a control input, and a switched resistor-capacitor (RC) network. The primary winding receives the single-ended signal and the secondary winding outputs the differential signals. The control input receives a control signal and the switched RC network tunes an output imbalance of the balun responsive to this control signal. The detector detects the output imbalance and the controller generates the control signal to control the switched RC network to reduce that output imbalance. The circuit produces well balanced differential signals over a wide range of signal frequencies, even when asymmetries, process variations, or parasitic capacitance in the balun would otherwise result in imbalance.

Abstract: Active transmitter leakage cancellation techniques are disclosed, for reducing transmitter leakage in a frequency-duplexing radio transceiver. Reducing transmitter leakage to the receiver path of a duplex transceiver eases the linearity requirements for low-noise amplifier and mixer circuits, potentially reducing transceiver cost as well as complexity. In an exemplary method, a radio-frequency (RF) cancellation signal is generated from a transmitter signal, and the RF cancellation signal is combined with a received RF signal to obtain a combined RF signal comprising a residual transmitter leakage component. The residual transmitter leakage component of the combined RF signal is converted, using, e.g., a frequency mixer, to obtain a down-converted signal at baseband or at an intermediate frequency.

Abstract: A tuning method and circuit for an LC tank resonant circuit, including an inductor and a variable capacitor, are described. In a tuning mode, an RF input signal is applied to an input port of the circuit, and the RF output signal is monitored as a variable capacitor control input is varied. A peak output is detected, and the corresponding variable capacitor control input is stored, and applied to the variable capacitor in an operating mode. In one embodiment, the variable capacitor control input is adjusted for delay in the peak detection process. In one embodiment, the variable capacitor comprises a coarse capacitor and a fine capacitor; the tuning procedure is repeated for each capacitor; and both coarse and fine variable capacitor control inputs are stored and applied to the respective capacitors in operating mode.

Abstract: According to one embodiment, a radio frequency receiver includes a quadrature mixer for converting radio frequency signals to baseband signals or intermediate frequency signals. The quadrature mixer includes an in-phase passive mixer and a quadrature-phase passive mixer. Each passive mixer includes a mixer core having a plurality of mixer input switch transistors and a plurality of output switch transistors connected to the mixer input switch transistors. Clock circuitry generates a first set of clock signals and a second set of clock signals. The first set of clock signals has a frequency twice that of the second set of clock signals. The first set of clock signals is arranged to drive the mixer input switch transistors and the second set of clock signals is arranged to drive the output switch transistors.