Patents by Inventor Fenghao Mu

Fenghao Mu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110199142
    Abstract: A clock generator circuit generates a wanted RF clock signal by using an up-converter, a spurious tone cancellation circuit, a controller, and at least two clock driver/dividers. The spurious tone cancellation circuit includes a tone detection circuit and a tone generation circuit. The up-converter mixes modulation signals with local quadrature RF clock signals to create an up-converted signal having a frequency tone equal to a desired frequency of the wanted RF clock signal. The first clock driver/divider amplifies and clips the up-converted signal into a first-clipped clock signal. The tone detection circuit detects the amplitude and phase of unwanted tones of the first-clipped clock signal in the baseband domain and provides information to the controller, which controls the tone generation circuit to cancel the unwanted tones and create a compensated version of first-clipped clock signal.
    Type: Application
    Filed: February 18, 2010
    Publication date: August 18, 2011
    Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventor: Fenghao MU
  • Publication number: 20110200076
    Abstract: A clock generator circuit may generate a target clock signal and may include a pattern generator to generate a pre-distorted version of a modulation signal from patterns stored by the pattern generator. An up-converter may up-convert the pre-distorted version of the modulation signal and a radio frequency lock oscillator signal to obtain an RF clock signal having a desired frequency tone. A tone detection circuit may receive the RF clock signal and detect a presence of unwanted tones. A controller may write the patterns corresponding to the pre-distorted version of the modulation signal to the pattern generator based on the detected unwanted tones in the RF clock signal.
    Type: Application
    Filed: February 18, 2010
    Publication date: August 18, 2011
    Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Fenghao MU, Henrik SJOLAND
  • Patent number: 7978009
    Abstract: A digital modulated power amplifier unit includes a differential radio frequency (RF) amplifier circuit having differential output nodes, a digital modulation signal input and complimentary clock signal inputs. The differential RF amplifier circuit includes a first pair of transistors operable to receive a digital modulation signal and a second pair of transistors operable to receive complimentary clock signals. The digital modulated power amplifier unit further includes an impedance compensation circuit connected between the differential output nodes of the differential RF amplifier circuit. The impedance compensation circuit includes a transistor connected in series between first and second RC circuits. The transistor is operable to electrically connect and disconnect the first RC circuit and the second RC circuit responsive to the digital modulation signal.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: July 12, 2011
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Fenghao Mu
  • Publication number: 20110103508
    Abstract: A digital affine transformation modulator and power amplifier drives a transmitter antenna. The modulator performs an affine transformation on a signal, wherein the I, Q space is mapped to a plurality of sectors. A signal in a sector is expressed as the sum of two vectors, the angles of which define the sector boundaries. A digital power amplifier comprises a plurality of amplifier cells, each cell comprising at least two amplifier units. For a given signal, each amplifier unit selectively amplifies a clock signal having a phase corresponding to one of the boundary angles of the signal's affine transformed sector. A subset of the plurality of amplifier cells receiving each phase clock signal are enabled, based on the magnitude of the associated vector describing the signal in affine transform space. The modulation scheme exhibits higher efficiency than quadrature modulation, without the bandwidth expansion and group delay mismatch of polar modulation.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 5, 2011
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Fenghao Mu, Sven Mattisson
  • Patent number: 7902937
    Abstract: A differential positive coefficient weighted quadrature modulator is actuated responsive to quadrature clock signals and positive digital modulation signals input to the modulator. The modulator includes an I-channel positive coefficient weighted modulator (PCWM) and a Q-channel PCWM. The I-channel PCWM has differential output nodes configured to output a differential I-channel signal responsive to the state of first and second positive digital modulation signals and first and second complimentary quadrature clock signals input to the I-channel PCWM. The Q-channel PCWM has differential output nodes configured to output a differential Q-channel signal responsive to the state of third and fourth positive digital modulation signals and third and fourth complimentary quadrature clock signals input to the Q-channel PCWM.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: March 8, 2011
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Fenghao Mu
  • Publication number: 20110026638
    Abstract: A differential positive coefficient weighted quadrature modulator is actuated responsive to quadrature clock signals and positive digital modulation signals input to the modulator. The modulator includes an I-channel positive coefficient weighted modulator (PCWM) and a Q-channel PCWM. The I-channel PCWM has differential output nodes configured to output a differential I-channel signal responsive to the state of first and second positive digital modulation signals and first and second complimentary quadrature clock signals input to the I-channel PCWM. The Q-channel PCWM has differential output nodes configured to output a differential Q-channel signal responsive to the state of third and fourth positive digital modulation signals and third and fourth complimentary quadrature clock signals input to the Q-channel PCWM.
    Type: Application
    Filed: August 3, 2009
    Publication date: February 3, 2011
    Inventor: Fenghao Mu
  • Publication number: 20110025415
    Abstract: A digital modulated power amplifier unit includes a differential radio frequency (RF) amplifier circuit having differential output nodes, a digital modulation signal input and complimentary clock signal inputs. The differential RF amplifier circuit includes a first pair of transistors operable to receive a digital modulation signal and a second pair of transistors operable to receive complimentary clock signals. The digital modulated power amplifier unit further includes an impedance compensation circuit connected between the differential output nodes of the differential RF amplifier circuit. The impedance compensation circuit includes a transistor connected in series between first and second RC circuits. The transistor is operable to electrically connect and disconnect the first RC circuit and the second RC circuit responsive to the digital modulation signal.
    Type: Application
    Filed: December 3, 2009
    Publication date: February 3, 2011
    Inventor: Fenghao Mu
  • Publication number: 20100284446
    Abstract: In one or more embodiments taught herein, a multi-band MIMO repeater is configured to translate normal wireless mobile bands into other frequency bands in the physical layer. An advantageous, multi-hop repeater chain includes two or more such repeaters, for propagating downlink signals from a base station, and for propagating uplink signals to the base station. Each such repeater may use paralleled homodyne structure transceivers for better SNR, spectrum combiners for uplink signal aggregation, spectrum separators for downlink signal de-aggregation, water mark signal inserters for optimization, and, among other things, spectrum analyzers for frequency band selection. In at least one such embodiment, a multi-hop repeater chain is configured for MIMO operation in an LTE Advanced or other MIMO network, to deliver high data rate over larger distances—e.g., further away from cell base stations.
    Type: Application
    Filed: December 16, 2009
    Publication date: November 11, 2010
    Inventors: Fenghao Mu, Stefan Andersson
  • Publication number: 20100253442
    Abstract: A tuning method and circuit for an LC tank resonant circuit, including an inductor and a variable capacitor, are described. In a tuning mode, an RF input signal is applied to an input port of the circuit, and the RF output signal is monitored as a variable capacitor control input is varied. A peak output is detected, and the corresponding variable capacitor control input is stored, and applied to the variable capacitor in an operating mode. In one embodiment, the variable capacitor control input is adjusted for delay in the peak detection process. In one embodiment, the variable capacitor comprises a coarse capacitor and a fine capacitor; the tuning procedure is repeated for each capacitor; and both coarse and fine variable capacitor control inputs are stored and applied to the respective capacitors in operating mode.
    Type: Application
    Filed: April 2, 2009
    Publication date: October 7, 2010
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Fenghao Mu
  • Publication number: 20100203860
    Abstract: The second-order inter-modulation distortion, originating in a differential passive mixer core from imbalance between devices, is reduced by compensating for the mismatch or load, by means of tuning the differential output impedance at the mixer core, or the input impedance of a filter coupled to the output of the passive mixer. Compensating for the imbalance allows greater suppression of even-order harmonics in the differential structure, which reduces second-order intermodulation at the output of the mixers. The compensation is achieved by tunable resistive elements that are calibrated by a built-in self-test architecture. The calibration circuit is deactivated during receiver operation.
    Type: Application
    Filed: February 10, 2009
    Publication date: August 12, 2010
    Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Fredrik Tillman, Fenghao Mu
  • Patent number: 7714759
    Abstract: A resistor network digital-to-analog converter (DAC) subdivides each sampling clock cycle of the DAC into a number of phases. For at least one bit input of the DAC associated with a desired input resistor weight, the input bit value is sampled at each phase. Each of those sampled values is then applied to a respective resistor branch, the parallel set of resistor branches forming the parallel equivalent of the desired input resistor weight for that bit input. Such application may be, for example, via a slew-rate controlled driver, to smooth transient edges in the generated analog output signal. The resulting analog signal experiences reduced reconstruction errors at a higher frequency while consuming less power than a comparable oversampling DAC. Shifting reconstruction errors to higher frequencies relaxes downstream filtering requirements, which simplifies analog signal filtering and allows, for example, the use of current-mode low pass filters.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: May 11, 2010
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Fenghao Mu
  • Publication number: 20100097253
    Abstract: A resistor network digital-to-analog converter (DAC) subdivides each sampling clock cycle of the DAC into a number of phases. For at least one bit input of the DAC associated with a desired input resistor weight, the input bit value is sampled at each phase. Each of those sampled values is then applied to a respective resistor branch, the parallel set of resistor branches forming the parallel equivalent of the desired input resistor weight for that bit input. Such application may be, for example, via a slew-rate controlled driver, to smooth transient edges in the generated analog output signal. The resulting analog signal experiences reduced reconstruction errors at a higher frequency while consuming less power than a comparable oversampling DAC. Shifting reconstruction errors to higher frequencies relaxes downstream filtering requirements, which simplifies analog signal filtering and allows, for example, the use of current-mode low pass filters.
    Type: Application
    Filed: October 20, 2008
    Publication date: April 22, 2010
    Inventor: Fenghao Mu
  • Publication number: 20100081408
    Abstract: A configurable passive mixer is described herein. According to one exemplary embodiment, the passive mixer comprises a clock generator, a controller, and a plurality of passive mixer cores connected in parallel. The clock generator comprises a local oscillator drive unit for each passive mixer core. The controller varies an effective transistor size of the passive mixer by separately configuring each of the passive mixer cores to enable/disable each passive mixer core. For example, the controller may selectively enable one or more of the passive mixer cores to vary the effective transistor width of the passive mixer. As the performance requirements and/or the operating communication standard change, the controller may re-configure each passive mixer core.
    Type: Application
    Filed: October 1, 2008
    Publication date: April 1, 2010
    Applicant: Telefonaktienbolaget LM Ericsson (publ)
    Inventors: Fenghao Mu, Fredrik Tillman
  • Publication number: 20100066442
    Abstract: According to the teachings presented herein, a tunable current-mode filter is implemented using two or more tunable filter stages in cascade connection. For example, a number of tunable filter stages corresponding to a desired filter order are included in the filter in cascade connection. Use of the current-mode filter simplifies circuit design, particularly in communication transmitter applications, and avoids current-to-voltage conversions needed when voltage-mode filters are used in current-mode signal processing chains. A method and circuit to tune and calibrate the frequency response of the filter are disclosed as well.
    Type: Application
    Filed: September 15, 2008
    Publication date: March 18, 2010
    Inventor: Fenghao Mu
  • Publication number: 20090268849
    Abstract: According to one embodiment, a radio frequency receiver comprises a quadrature mixer configured to convert radio frequency signals to baseband signals or intermediate frequency signals. The quadrature mixer comprises an in-phase passive mixer and a quadrature-phase passive mixer. Each passive mixer comprises a mixer core having a plurality of mixer input switch transistors and a plurality of output switch transistors connected to the mixer input switch transistors. Clock circuitry generates a plurality of quadrature pulsed clock signals and delayed versions of the quadrature pulsed clock signals. The quadrature pulsed clock signals and the delayed versions of the quadrature pulsed clock signals drive the mixer input switch transistors and the output switch transistors.
    Type: Application
    Filed: April 23, 2008
    Publication date: October 29, 2009
    Inventors: Fenghao Mu, Fredrik Tillman
  • Publication number: 20090270062
    Abstract: According to one embodiment, a radio frequency receiver includes a quadrature mixer for converting radio frequency signals to baseband signals or intermediate frequency signals. The quadrature mixer includes an in-phase passive mixer and a quadrature-phase passive mixer. Each passive mixer includes a mixer core having a plurality of mixer input switch transistors and a plurality of output switch transistors connected to the mixer input switch transistors. Clock circuitry generates a first set of clock signals and a second set of clock signals. The first set of clock signals has a frequency twice that of the second set of clock signals. The first set of clock signals is arranged to drive the mixer input switch transistors and the second set of clock signals is arranged to drive the output switch transistors.
    Type: Application
    Filed: April 23, 2008
    Publication date: October 29, 2009
    Inventors: Fenghao Mu, Fredrik Tillman
  • Patent number: 7599675
    Abstract: A frequency conversion receiver comprises a passive mixer, a Low-Noise Amplifier (LNA) and a balun. The low-noise amplifier generates an amplified single-ended signal responsive to a single-ended receiver input signal. The passive mixer generates a mixer output signal responsive to a differential mixer input signal and a four-phase local oscillator signal. The balun transforms the amplified singled-ended signal into the differential mixer input signal, the balun having a first winding coupled to an output of the low-noise amplifier and a second winding coupled to an input of the passive mixer, the second winding having more turns than the first winding. The turn ratio of the second winding to the first winding provides gain compensation to the low-noise amplifier, and in conjunction with the low-noise amplifier and the passive mixer, provides a desired gain to the receiver and linearity over a dynamic range of the receiver input signal.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: October 6, 2009
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Fenghao Mu, Andreas T. Mårtensson, Magnus Nilsson
  • Publication number: 20090213770
    Abstract: Active transmitter leakage cancellation techniques are disclosed, for reducing transmitter leakage in a frequency-duplexing radio transceiver. Reducing transmitter leakage to the receiver path of a duplex transceiver eases the linearity requirements for low-noise amplifier and mixer circuits, potentially reducing transceiver cost as well as complexity. In an exemplary method, a radio-frequency (RF) cancellation signal is generated from a transmitter signal, and the RF cancellation signal is combined with a received RF signal to obtain a combined RF signal comprising a residual transmitter leakage component. The residual transmitter leakage component of the combined RF signal is converted, using, e.g., a frequency mixer, to obtain a down-converted signal at baseband or at an intermediate frequency.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 27, 2009
    Inventor: Fenghao Mu
  • Patent number: 7486135
    Abstract: A configurable LNA architecture for a multi-band RF receiver front end comprises a bank of LNAs, each optimized to a different frequency band, wherein each LNA has a configurable topology. Each LNA comprises a plurality of amplifier stages, each stage including an RF transistor having a different width. The transistor widths in adjacent amplifier stages may be binary weighted, or may be sized to achieve a constant gain step. By selectively enabling and disabling RF transistors, the effective transistor width of the LNA can be controlled with a fine granularity. A DAC generates a bias voltage with a small quantization step, additionally providing a fine granularity of gain control. The LNAs are protected by overvoltage protection circuits which shield transistors from a supply voltage in excess of their breakdown voltage. A source degeneration inductor presents a real resistance at inputs of the LNAs, without introducing thermal noise.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: February 3, 2009
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Fenghao Mu
  • Publication number: 20080297259
    Abstract: A configurable LNA architecture for a multi-band RF receiver front end comprises a bank of LNAs, each optimized to a different frequency band, wherein each LNA has a configurable topology. Each LNA comprises a plurality of amplifier stages, each stage including an RF transistor having a different width. The transistor widths in adjacent amplifier stages may be binary weighted, or may be sized to achieve a constant gain step. By selectively enabling and disabling RF transistors, the effective transistor width of the LNA can be controlled with a fine granularity. A DAC generates a bias voltage with a small quantization step, additionally providing a fine granularity of gain control. The LNAs are protected by overvoltage protection circuits which shield transistors from a supply voltage in excess of their breakdown voltage. A source degeneration inductor presents a real resistance at inputs of the LNAs, without introducing thermal noise.
    Type: Application
    Filed: May 29, 2007
    Publication date: December 4, 2008
    Inventor: Fenghao Mu