Abstract: Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

Abstract: Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

Abstract: Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

Abstract: Techniques for improving the conductivity of copper (Cu)-filled vias are provided. In one aspect, a method of fabricating a Cu-filled via is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A thin seed Cu layer is deposited on the Ru layer. A first anneal is performed to increase a grain size of the seed Cu layer. The via is filled with additional Cu. A second anneal is performed to increase the grain size of the additional Cu.

Abstract: Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

Abstract: Techniques for improving the conductivity of copper (Cu)-filled vias are provided. In one aspect, a method of fabricating a Cu-filled via is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A thin seed Cu layer is deposited on the Ru layer. A first anneal is performed to increase a grain size of the seed Cu layer. The via is filled with additional Cu. A second anneal is performed to increase the grain size of the additional Cu.

Abstract: Techniques for nitridation of copper (Cu) wires. In one aspect, a method for nitridation of a Cu wire is provided. The method includes the following step. The Cu wire and trimethylsilylazide (TMSAZ) in a carrier gas are contacted at a temperature, pressure and for a length of time sufficient to form a nitridized layer on one or more surfaces of the Cu wire. The Cu wire can be part of a wiring structure and can be embedded in a dielectric media. The dielectric media can comprise an ultra low-k dielectric media.

Abstract: Techniques for forming a ruthenium (Ru) capping layer on a copper (Cu) wire are provided. In one aspect, a method of forming a Ru capping layer on at least one exposed surface of a Cu wire embedded in a dielectric structure includes the following steps. A first Ru layer is selectively deposited onto the Cu wire and the dielectric structure by chemical vapor deposition (CVD) for a period of time during which selective nucleation of the Ru occurs on the surface of the Cu wire. Any nucleated Ru present on the dielectric structure is oxidized. The oxidized Ru and an aqueous acid are contacted to remove the oxidized Ru from the dielectric structure based on a selectivity of the aqueous acid in dissolving the oxidized Ru. A second Ru layer is selectively deposited onto the first Ru layer by CVD to produce a thicker Ru layer.

Abstract: The present invention is directed to an alpha-W layer which is employed in interconnect structures such as trench capacitors or damascene wiring levels as a diffusion barrier layer. The alpha-W layer is a single phased material that is formed by a low temperature/pressure chemical vapor deposition process using tungsten hexacarbonyl, W(CO)6, as the source material.

Abstract: A deposition member adapted for discharging a deposition material during a deposition process can acquire a coating during the deposition. Such an initial emissivity value is selected for the deposition member, before any of the coating became deposited, that the emissivity of the deposition member remains substantially unchanged during the deposition process. In a representative embodiment the deposition member is coated with an appropriate thin layer for achieving the selected emissivity value.

Abstract: A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

Abstract: An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; a barrier layer located in the via opening; an interlayer of palladium and/or platinum on the barrier layer; and a layer of copper or copper alloy on the interlayer is provided.

Abstract: The barrier material of the invention provides for the electrodeposition of copper. The barrier layer includes a dielectric interface surface region, and a copper interface surface region with at least 50 atom percent of a copper interface metal. In particular, the barrier layer of the invention provides for the electrodeposition of copper or copper alloy directly onto the copper interface region of the barrier layer in a direct electrodeposition process. The process includes providing a dielectric layer disposed on an underlayer, contacting a barrier layer to the dielectric layer, and depositing a conducting layer onto the barrier layer.

Abstract: A barrier material that is particularly suited as a barrier layer in copper interconnects structures found in semiconductor structures. The barrier layer contains one or more regions with one region containing at least 50 atom percent of a copper interface metal. The copper interface metal is selected from ruthenium, rhodium, palladium, silver, gold, platinum, iridium, selenium, tellurium, or alloys thereof. The barrier layer also contains a dielectric interface material.

Abstract: A process of passivating a metal-gated CMOS structure in which a metal-gated CMOS structure is passivated in an atmosphere of molecular hydrogen at a temperature of between about 250° C. and about 500° C. and a pressure of at least about 200 Torr. The present process provides a lower interface state density than obtainable by prior art passivation processes.

Abstract: A novel photodetector CMOS-compatible photodetector is disclosed in which photo-generation of carriers (electrons) is carried out in the metal of the electrodes, rather than as electron-hole pairs in the semiconductor on which the metal electrodes are deposited. The novel photo detector comprises a silicon or other semiconductor substrate material characterized by an electron energy bandgap, and a pair of metal electrodes disposed upon a surface of the silicon to define therebetween a border area of the surface. One of the two electrodes being exposed to the incident radiation and covering an area of said surface which is larger than the aforesaid border area, the aforesaid metal of the electrodes being characterized by a Fermi level which is within said electron energy bandgap.

Abstract: A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

Abstract: An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; a barrier layer located in the via opening; an interlayer of palladium and/or platinum on the barrier layer; and a layer of copper or copper alloy on the interlayer is provided.

Abstract: The present invention relates to a method and apparatus for ensuring uniform and reproducible heating of a deformation-tolerant substrate during low-pressure chemical vapor deposition (CVD) of a metal film on a surface of the substrate. The uniform and reproducible heating of the substrate is achieved in the present invention by positioning the substrate on a beveled surface of a chamfered ring which is located above the heating element in a CVD reactor chamber. The space between heating element, chamfered ring and bottom surface of the substrate define a cavity between the substrate and heating element that ensures that the substrate is heated by radiative means rather than direct contact.

Abstract: The present invention discloses a method for forming a layer of nitrogen and silicon containing material on a substrate by first providing a heated substrate and then flowing a gas which has silicon and nitrogen atoms but no carbon atoms in the same molecule over said heated substrate at a pressure of not higher than 500 Torr, such that a layer of nitrogen and silicon containing material is formed on the surface. The present invention is further directed to a composite structure that includes a substrate and a layer of material containing nitrogen and silicon but not carbon overlying the substrate for stopping chemical species from reaching the substrate. The present invention is further directed to a structure that includes a semiconducting substrate, a gate insulator on the substrate, a nitrogen-rich layer on top of the gate insulator, and a gate electrode on the nitrogen-rich layer, wherein the nitrogen-rich layer blocks diffusion of contaminating species from the gate electrode to the gate insulator.