Abstract: A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.

Abstract: Techniques and mechanisms to mitigate corrosion to via structures of a composite chiplet. In an embodiment, a composite chiplet comprises multiple integrated circuit (IC) components which are each in a different respective one of multiple levels. One or more conductive vias extend through an insulator layer in a first level of the multiple levels. An annular structure of the composite chiplet extends vertically through the insulator layer, and surrounds the one or more conductive vias in the insulator layer. The annular structure mitigates an exposure of the one or more conductive vias to moisture which is in a region of the insulator layer that is not surrounded by the annular structure. In another embodiment, the annular structure further surrounds an IC component which extends in the insulator layer.

Abstract: Various aspects may provide a handling assembly. The handling assembly may include a body with a component-handling surface. The component-handling surface may include a first component-handling region configured to accommodate a first semiconductor component arrangement and a second component-handling region configured to accommodate a second semiconductor component arrangement. The handling assembly may further include an electrode arrangement disposed at the body in a manner so as to be capable of independently toggling each of the first component-handling region and the second component-handling region between an active state and an inactive state. In the active state the electrode arrangement may provide an electrostatic retention force over the component-handling region, configured to retain a corresponding semiconductor component arrangement on the component-handling region.

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.

Abstract: A die assembly comprising: a first component layer having conductive through-connections in an insulator, a second component layer comprising a die, and an active device layer (ADL) at an interface between the first component layer and the second component layer. The ADL comprises active elements electrically coupled to the first component layer and the second component layer. The die assembly further comprises a bonding layer electrically coupling the ADL to the second component layer. In some embodiments, the die assembly further comprises another ADL at another interface between the first component layer and a package support opposite to the interface. The first component layer may comprise another die having through-substrate vias (TSVs). The die and the another die may be fabricated using different process nodes.

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component, including an organic dielectric material; a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes metal contacts and a dielectric material between adjacent ones of the metal contacts, and wherein the dielectric material includes an inorganic dielectric material; and a third microelectronic component coupled to the first microelectronic component by wire bonding or solder.

Abstract: In some embodiments, pick and place tools can pick and place multiple dies with different die sizes from different source wafers at a time to increase the throughput. In addition, some of these tools may incorporate non-contact die handling during pick and place processes. In some examples, the non-contact mechanisms can use Bernoulli effects or acoustic wave or vibration techniques to hold and release dies.

Abstract: Heat sink incorporation in integrated circuit layers using high accuracy bonding is described. In an example, an integrated circuit structure includes a first device layer. A second device layer is below the first device layer. An interconnect structure is between the first device layer and the second device layer. A heat sink material layer is between the interconnect structure and the second device layer.

Abstract: Device stacking in integrated circuit layers using high accuracy bonding is described. In an example, an integrated circuit structure includes a first device layer above a first interconnect structure, the first device layer including nanowire-based transistors or fin-based transistors. The integrated circuit structure includes a second device layer below a second interconnect structure, the second device layer including nanowire-based transistors or fin-based transistors, and the second interconnect structure bonded directly to the first interconnect structure.

Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include an interconnect die in a first layer surrounded by a dielectric material; a processor integrated circuit (processor IC) and an integrated circuit (IC) in a second layer, the second layer on the first layer, wherein the interconnect die is electrically coupled to the processor IC and the IC by first interconnects having a pitch of less than 10 microns between adjacent first interconnects; a photonic integrated circuit (PIC) and a substrate in a third layer, the third layer on the second layer, wherein the PIC has an active surface, and wherein the active surface of the PIC is coupled to the IC by second interconnects having a pitch of less than 10 microns between adjacent second interconnects; and a fiber connector optically coupled to the active surface of the PIC.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die; a second die and a third die, the second and third dies having a first surface and an opposing second surface, the first surfaces of the second and third dies electrically coupled to the first die, and the third die including voltage regulator circuitry; a first material around the second and third dies, the first material having a non-planar surface; a second material, on the non-planar surface of the first material and the second surfaces of the second and third dies, having a thermal conductivity greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns; and a redistribution layer (RDL) on and coupled to the second material, the RDL including a conductive pathway electrically coupled to the second and third dies by interconnects.

Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a metal matrix composite layer on the backside surface, wherein the metal matrix composite layer has a filler material disposed therein to reduce the coefficient of thermal expansion thereof. The filler material may be a plurality of graphitic carbon filler particles, wherein the plurality of graphitic carbon filler particles has an average aspect ratio of greater than about 10, or the filler material may be a plurality of diamond particles, wherein the filler material is clad with a metal material.

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate comprising one or more conductive interconnect structures on a surface of the substrate. One or more support features are on one or more peripheral regions of the surface of the substrate. A first side of a die is coupled to the one or more conductive interconnect structures and is over the one or more support features. A die backside layer is on the second side of the die.

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate having one or more solder structures. A first set of solder structures is located in a peripheral region of the substrate and a second set of solder structures is located in a central region of the substrate. A height of individual ones of the second set of solder structures is greater than a height of individual ones of the first set of solder structures. A die having a first side and a second side includes one or more conductive die pads on the first side, where individual ones of the conductive die pads are on individual ones of the first set solder structures and on individual ones of the second set solder structures. A die backside layer is on the second side of the die.

Abstract: Reusable composite stencils for spray processes, particularly for spray processes used in the fabrication of integrated circuit devices, may be fabricated having a permanent core and at least one sacrificial material layer. Thus, in operation, when a predetermined amount of the sacrificial material layer has been ablated away by a material being sprayed in the spray process, the remaining sacrificial material layer may be removed and reapplied to its original thickness. Therefore, the permanent core, which is usually expensive and/or difficult to fabricate, may be repeatedly reused.

Abstract: Composite IC die structures comprising a first IC die that has a first region directly bonded to a second IC die across a hybrid-bond interface and a topographic feature extending from a second region of the first IC die. In some examples, a hybrid bond interface is fabricated prior to forming a topographic IC die feature. In other examples, a hybrid bond interface is fabricated after forming a topographic IC die feature. A PIC die comprising a planar optical waveguide further includes an optical coupler protruding from a region of the die. In another region of the PIC die metallization features are embedded with a dielectric material suitable for forming a hybrid bond with a surface of an EIC die. Scaling of the directly bonded interconnections between the PIC and EIC die may facilitate further disintegration of the optical and electrical domains within a heterogenous chip/chiplet assembly.

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.

Abstract: Embodiments disclosed herein include an apparatus that includes a substrate with a first optical waveguide within the substrate, an optical ring resonator within the substrate, and a second optical waveguide within the substrate. In an embodiment, the first optical waveguide and the second optical waveguide are offset from each other in a vertical direction and a horizontal direction. In an embodiment, the optical ring resonator is between the first optical waveguide and the second optical waveguide in the horizontal direction.