Patents by Inventor Feras Eid

Feras Eid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190393131
    Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Publication number: 20190393193
    Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Publication number: 20190393118
    Abstract: A package is disclosed. The package includes a substrate, a die on the substrate, an integrated heat spreader on the substrate that encloses the die, the integrated heat spreader including a hole that extends through the integrated heat spreader, an air permeable adhesive contacting the integrated heat spreader and forming a cavity underneath the integrated heat spreader, and a liquid metal thermal interface material filling the cavity. A sealant plugs the hole that extends through the integrated heat spreader.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Inventors: Brandon M. RAWLINGS, Feras EID, Kelly LOFGREEN
  • Publication number: 20190393192
    Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Publication number: 20190385932
    Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 19, 2019
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Publication number: 20190385933
    Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 19, 2019
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Publication number: 20190385931
    Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 19, 2019
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Publication number: 20190385977
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 19, 2019
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Shawna M. Liff
  • Patent number: 10508961
    Abstract: A semiconductor package having an air pressure sensor and methods to form a semiconductor package having an air pressure sensor are described. For example, a semiconductor package includes a plurality of build-up layers. A cavity is disposed in one or more of the build-up layers. An air pressure sensor is disposed in the plurality of build-up layers and includes the cavity and an electrode disposed above the cavity.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: December 17, 2019
    Assignee: INTEL CORPORATION
    Inventors: Kevin L. Lin, Qing Ma, Feras Eid, Johanna Swan, Weng Hong Teh
  • Patent number: 10492267
    Abstract: Some forms relate to a stretchable computing display device. The stretchable computing display device includes a stretchable base; a patterned conductive section mounted on the stretchable base, wherein the patterned conductive section includes a first portion and a second portion that is electrically isolated from the first portion; an electroluminescent material mounted on the stretchable base such that the electroluminescent material is between the first portion and the second portion of the patterned conductive section; an encapsulant that covers at least a portion of the patterned conductive section; and a textile such that the stretchable base is mounted on the textile, wherein the textile is part of a garment.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Sasha Oster, Nadine L. Dabby, Aleksandar Aleksov, Braxton Lathrop, Feras Eid
  • Publication number: 20190355636
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
  • Patent number: 10475736
    Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Arnab Sarkar, Arghya Sain, Kristof Darmawikarta, Henning Braunisch, Prashant D. Parmar, Sujit Sharan, Johanna M. Swan, Feras Eid
  • Publication number: 20190343017
    Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device, and at least one unidirectional heat transfer device between the first integrated circuit device and the second integrated circuit device. In one embodiment, the unidirectional heat transfer device may be oriented such that it has a higher conductivity in the direction of heat transfer from the first integrated circuit device to the second integrated circuit device than it does in the opposite direction. When the temperature of the second integrated circuit device rises above the temperature of the first integrated circuit device, the unidirectional heat transfer device will act as a thermal insulator, and when the temperature of the first integrated circuit device rises above the temperature of the second integrated circuit device, the unidirectional heat transfer device will act as a thermal conductor.
    Type: Application
    Filed: May 3, 2018
    Publication date: November 7, 2019
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Publication number: 20190326192
    Abstract: A heat dissipation device may be formed as a thermally conductive structure having at least one thermal isolation structure extending at least partially through the thermally conductive structure. The heat dissipation device may be thermally connected to a plurality of integrated circuit devices, such that the at least one thermal isolation structure is positioned between at least two integrated circuit devices. The heat dissipation device allows for heat transfer away from each of the plurality of integrated circuit devices, such as in a z-direction within the thermally conductive structure, while substantially preventing heat transfer in either the x-direction and/or the y-direction within the thermally isolation structure, such that thermal cross-talk between integrated circuit devices is reduced.
    Type: Application
    Filed: April 19, 2018
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Publication number: 20190323785
    Abstract: A heat dissipation device may be formed having at least one isotropic thermally conductive section (uniformly high thermal conductivity in all directions) and at least one anisotropic thermally conductive section (high thermal conductivity in at least one direction and low thermal conductivity in at least one other direction). The heat dissipation device may be thermally coupled to a plurality of integrated circuit devices such that at least a portion of the isotropic thermally conductive section(s) and/or the anisotropic thermally conductive section(s) is positioned over at least one integrated circuit device.
    Type: Application
    Filed: April 19, 2018
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Patent number: 10453635
    Abstract: An electronic device and methods including a switch formed in a chip package are shown. An electronic device and methods including a switch formed in a polymer based dielectric are shown. Examples of switches shown include microelectromechanical system (MEMS) structures, such as cantilever switches and/or shunt switches.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Qing Ma, Johanna Swan, Valluri Rao, Feras Eid
  • Publication number: 20190311980
    Abstract: Disclosed herein are microelectronic assemblies with integrated perovskite layers, and related devices and methods. For example, in some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, and a perovskite conductive layer on the conductive layer. In some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, a perovskite conductive layer having a first crystalline structure on the conductive layer, and a perovskite dielectric layer having a second crystalline structure on the perovskite conductive layer. In some embodiments, the first and second crystalline structures have a same orientation.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 10, 2019
    Applicant: Intel Corporation
    Inventors: Feras Eid, Shawna M. Liff, Thomas Sounart, Johanna M. Swan
  • Publication number: 20190297975
    Abstract: Embodiments of the invention include an active venting system. According to an embodiment of the invention, the active venting system may include a substrate having one or more seams formed through the substrate. In order to open the vents defined by the seams through the substrate, a piezoelectric layer may be formed proximate to one or more of the seams. Additional embodiments may include a first electrode and a second electrode that contact the piezoelectric layer in order to provide a voltage differential across the piezoelectric layer. In an embodiment the active venting system may be integrated into a garment. In such an embodiment, the garment may also include an electronics module for controlling the actuators. Additionally, conductive traces may be printed on the garment or sewn into the garment to provide electrical connections from the electronics module to each of the piezoelectric actuators.
    Type: Application
    Filed: July 2, 2016
    Publication date: October 3, 2019
    Inventors: Aleksandar ALEKSOV, Sasha N. OSTER, Feras EID, Shawna M. LIFF, Thomas L. SOUNART, Johanna M. SWAN, Baris BICEN, Valluri R. RAO
  • Patent number: 10432167
    Abstract: Embodiments of the invention include a piezoelectric resonator which includes an input transducer having a first piezoelectric material, a vibrating structure coupled to the input transducer, and an output transducer coupled to the vibrating structure. In one example, the vibrating structure is positioned above a cavity of an organic substrate. The output transducer includes a second piezoelectric material. In operation the input transducer causes an input electrical signal to be converted into mechanical vibrations which propagate across the vibrating structure to the output transducer.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Feras Eid, Baris Bicen, Telesphor Kamgaing, Vijay K. Nair, Johanna M. Swan, Georgios C. Dogiamis, Valluri R. Rao
  • Patent number: 10424559
    Abstract: An embodiment includes an apparatus comprising: a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (W/(m·K)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity. Other embodiments are described herein.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Nader N. Abazarnia, Johanna M. Swan, Taesha D. Beasley, Sasha N. Oster, Tannaz Harirchian, Shawna M. Liff