Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include an interconnect die in a first layer surrounded by a dielectric material; a processor integrated circuit (processor IC) and an integrated circuit (IC) in a second layer, the second layer on the first layer, wherein the interconnect die is electrically coupled to the processor IC and the IC by first interconnects having a pitch of less than 10 microns between adjacent first interconnects; a photonic integrated circuit (PIC) and a substrate in a third layer, the third layer on the second layer, wherein the PIC has an active surface, and wherein the active surface of the PIC is coupled to the IC by second interconnects having a pitch of less than 10 microns between adjacent second interconnects; and a fiber connector optically coupled to the active surface of the PIC.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die; a second die and a third die, the second and third dies having a first surface and an opposing second surface, the first surfaces of the second and third dies electrically coupled to the first die, and the third die including voltage regulator circuitry; a first material around the second and third dies, the first material having a non-planar surface; a second material, on the non-planar surface of the first material and the second surfaces of the second and third dies, having a thermal conductivity greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns; and a redistribution layer (RDL) on and coupled to the second material, the RDL including a conductive pathway electrically coupled to the second and third dies by interconnects.

Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a metal matrix composite layer on the backside surface, wherein the metal matrix composite layer has a filler material disposed therein to reduce the coefficient of thermal expansion thereof. The filler material may be a plurality of graphitic carbon filler particles, wherein the plurality of graphitic carbon filler particles has an average aspect ratio of greater than about 10, or the filler material may be a plurality of diamond particles, wherein the filler material is clad with a metal material.

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate comprising one or more conductive interconnect structures on a surface of the substrate. One or more support features are on one or more peripheral regions of the surface of the substrate. A first side of a die is coupled to the one or more conductive interconnect structures and is over the one or more support features. A die backside layer is on the second side of the die.

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate having one or more solder structures. A first set of solder structures is located in a peripheral region of the substrate and a second set of solder structures is located in a central region of the substrate. A height of individual ones of the second set of solder structures is greater than a height of individual ones of the first set of solder structures. A die having a first side and a second side includes one or more conductive die pads on the first side, where individual ones of the conductive die pads are on individual ones of the first set solder structures and on individual ones of the second set solder structures. A die backside layer is on the second side of the die.

Abstract: Reusable composite stencils for spray processes, particularly for spray processes used in the fabrication of integrated circuit devices, may be fabricated having a permanent core and at least one sacrificial material layer. Thus, in operation, when a predetermined amount of the sacrificial material layer has been ablated away by a material being sprayed in the spray process, the remaining sacrificial material layer may be removed and reapplied to its original thickness. Therefore, the permanent core, which is usually expensive and/or difficult to fabricate, may be repeatedly reused.

Abstract: Composite IC die structures comprising a first IC die that has a first region directly bonded to a second IC die across a hybrid-bond interface and a topographic feature extending from a second region of the first IC die. In some examples, a hybrid bond interface is fabricated prior to forming a topographic IC die feature. In other examples, a hybrid bond interface is fabricated after forming a topographic IC die feature. A PIC die comprising a planar optical waveguide further includes an optical coupler protruding from a region of the die. In another region of the PIC die metallization features are embedded with a dielectric material suitable for forming a hybrid bond with a surface of an EIC die. Scaling of the directly bonded interconnections between the PIC and EIC die may facilitate further disintegration of the optical and electrical domains within a heterogenous chip/chiplet assembly.

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.

Abstract: Embodiments disclosed herein include an apparatus that includes a substrate with a first optical waveguide within the substrate, an optical ring resonator within the substrate, and a second optical waveguide within the substrate. In an embodiment, the first optical waveguide and the second optical waveguide are offset from each other in a vertical direction and a horizontal direction. In an embodiment, the optical ring resonator is between the first optical waveguide and the second optical waveguide in the horizontal direction.

Abstract: Embodiments disclosed herein include an apparatus that comprises a first layer with a first dielectric material, a second layer with a second dielectric material embedded within the first layer, where the second dielectric material has a higher index of refraction than the first dielectric material, and a first contact that is electrically conductive embedded in the first layer. In an embodiment, a third layer comprises a third dielectric material, a fourth layer comprising a fourth dielectric material and is embedded within the third layer, where the fourth dielectric material has a higher index of refraction than the third dielectric material, and a second contact that is electrically conductive embedded in the third layer. In an embodiment, the first layer directly contacts the third layer, the second layer directly contacts the fourth layer, and the first contact directly contacts the second contact.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die; a second die and a third die electrically coupled to the first die; a dielectric material, around the second die and the third die, having a non-planar surface; a first material, on the non-planar surface of the dielectric material and on the second die and the third die, having a thermal conductivity greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns; a second material, on the first material, including titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, or silicon, carbon, and nitrogen; and a third material, on the second material, having a thermal conductivity greater than 150 W/m-K and a thickness between 1 micron and 200 microns.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die having a first surface, an opposing second surface, and side surfaces between the first surface and the second surface, wherein the first surface of the second die is electrically coupled to the surface of the first die, and wherein the side surfaces of the second die are scalloped. In some embodiments, side surfaces of the second die may include a protective coating material, where the protective coating material includes an alkyl silane, a fluoroalkyl silane, a thiol, a phosphonic acid, an alkanoic acid, a siloxane, a silazane, a polyolefin, or a fluorinated polymer. In some embodiments, a microelectronic assembly may further include a dielectric material around a plurality of second dies and the dielectric material does not have an interface seam.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die and a third die, the second die and the third die having a first surface and an opposing second surface, wherein the first surfaces of the second die and the third die are electrically coupled to the surface of the first die; a first material on the surface of the first die and around and between the second die and the third die, the first material having a non-planar surface; and a layer on and in physical contact with the non-planar surface of the first material and with the second surfaces of the second die and the third die, the layer including a second material having a thermal conductivity equal to or greater than 10 watt per meter-kelvin (W/m-K).

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die and a third die, the second and third dies having a first surface and an opposing second surface, wherein the first surfaces of the second and third dies are electrically coupled to the surface of the first die; a first material on the surface of the first die and around and between the second and third dies, the first material having a non-planar surface; a layer on the non-planar surface of the first material and the second surfaces of the second and third dies, the layer including a second material having a thermal conductivity equal to or greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns; and a substrate, on the layer, including a microchannel.

Abstract: Devices and systems with shifted out-of-plane light propagation, and methods of forming the same, are disclosed herein. In one example, a microelectronic assembly includes a first optical waveguide, a second optical waveguide, and one or more passive optical components. The first and second optical waveguides are optically coupled via the passive optical components. Moreover, the passive optical components are to shift light propagation out of plane between the first and second optical waveguides.

Abstract: Photonics through vias, stacked photonic integrated circuit (PIC) die package assemblies, related apparatuses, systems, and methods of fabrication are disclosed. A PIC die has a first surface and opposing second surface and an opening extending between the first and second surfaces to define a sidewall of a substrate material of the PIC die, a photonics via is within the opening and has a first material on the sidewall and an optional second material within the first material. The refractive indices of the substrate material, first material, and optional second material are selected to provide total internal reflection for light waves within the photonics via.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die; a second die and a third die having a first surface and an opposing second surface, where the first surface of the second die is electrically coupled to the first die by interconnects and the first surface of the third die is electrically coupled to the first die by a bonding material, and the bonding material includes titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, or silicon, carbon, and nitrogen; a first material, around the second die and the third die, having a non-planar surface; and a second material, on the non-planar surface of the first material and on the second and third dies, having a thermal conductivity greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns.

Abstract: Multi-tiered photonic integrated circuit (PIC) die package assemblies, and related apparatuses, systems, and methods of fabrication are disclosed. A package assembly includes a lower tier having a base PIC die, which provides at least some functionality of a PIC core or unit. A photonics coupler is in an upper tier of the package assembly and optically connects the assembly to external optical devices. At least one middle tier of the package assembly, between the base PIC die and the photonics coupler, includes PIC die(s), electronic integrated circuit (EIC) die(s), or hybrid photonic and electronic IC (hybrid IC) die(s), or combinations thereof. The middle tier die(s) may provide the remaining functionality of the PIC core or unit. A photonics via extends vertically through the middle tier and optically couples the PIC die and the photonics coupler.

Abstract: Technologies for a compact and low-crosstalk multilayer waveguide stack are disclosed. In an illustrative embodiment, a photonic integrated circuit (PIC) die includes a 3D array of waveguides arranged in a multilayer stack. Individual waveguides have a propagation constant different from the propagation constant of neighboring waveguides, which can reduce crosstalk between neighboring waveguides. In an illustrative embodiment, the propagation constant can be controlled by changing the width of individual waveguides. In other embodiments, the propagation constant can be controlled by changing any suitable parameter, such as the height of the waveguides, the core of the waveguides, the cladding of the waveguides, etc.