Patents by Inventor Feras Eid

Feras Eid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250108459
    Abstract: An embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the third layer comprising a plurality of integrated circuit (IC) components, and applying a laser to ablate portions of the first layer, wherein the second layer protects the third layer from cracking during application of the laser.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: INTEL CORPORATION
    Inventors: Andrey Vyatskikh, Feras Eid, Tushar Kanti Talukdar, Kimin Jun, Thomas L. Sounart, Jeffery D. Bielefeld, Grant M. Kloster, Carlos Bedoya Arroyave, Golsa Naderi, Adel Elsherbini
  • Publication number: 20250109221
    Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region surrounded by hydrophobic structures that include a cross-linked material. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The cross-linked material hydrophobic structures contain the liquid droplet for alignment and are resistant to plasma treatment prior to bonding.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Wenhao Li, Veronica Strong, Feras Eid, Bhaskar Jyoti Krishnatreya
  • Publication number: 20250112177
    Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die backside surface and a surface of a structural substrate each include bonding regions surrounded by hydrophobic structures. A liquid droplet is applied to the die or structural substrate bonding region and the die is placed on the bonding region of the structural substrate. Capillary forces cause the die to self-align to the bonding region, and a bond is formed by evaporating the liquid and subsequent anneal. A hybrid bond is then formed between the opposing active surface of the die and a base substrate using wafer-to-wafer bonding. IC structures including the IC die and portions of the structural substrate and base substrate are segmented from the bonded wafers and assembled.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Feras Eid, Thomas Sounart, Yi Shi, Michael Baker, Adel Elsherbini, Kimin Jun, Xavier Brun, Wenhao Li
  • Publication number: 20250112155
    Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by a protective layer and hydrophobic structures on the protective layer. The protective layer is formed prior to pre-bond processing to protect the hybrid bonding region during plasma activation, clean test, high temperature processing, or the like. Immediately prior to bonding, the hydrophobic structures are selectively applied to the protective layer. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The hydrophobic structures contain the liquid droplet for alignment during bonding.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Kimin Jun, Scott Clendenning, Feras Eid, Robert Jordan, Wenhao Li, Jiun-Ruey Chen, Tayseer Mahdi, Carlos Felipe Bedoya Arroyave, Shashi Bhushan Sinha, Anandi Roy, Tristan Tronic, Dominique Adams, William Brezinski, Richard Vreeland, Thomas Sounart, Brian Barley, Jeffery Bielefeld
  • Publication number: 20250112092
    Abstract: An embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the second layer comprising at least one integrated circuit (IC) component, the third layer comprising at least one dielectric material; and using a laser to weaken the first layer to facilitate separation of the second layer from the substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corportation
    Inventors: Thomas L. Sounart, Adel Elsherbini, Feras Eid, Tushar Kanti Talukdar, Andrey Vyatskikh
  • Publication number: 20250112077
    Abstract: An embodiment discloses an electronic device comprising an integrated circuit (IC) die, a stub extending from the IC die; and a mesa structure under the IC die, wherein the IC die and the stub are bonded to the mesa structure.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Feras Eid, Andrey Vyatskikh, Adel Elsherbini, Brandon M. Rawlings, Tushar Kanti Talukdar, Thomas L. Sounart, Kimin Jun, Johanna Swan, Grant M. Kloster, Carlos Bedoya Arroyave
  • Publication number: 20250112173
    Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Kimin Jun, Feras Eid, Adel Elsherbini, Thomas Sounart, Yi Shi, Wenhao Li
  • Publication number: 20250112127
    Abstract: A surface finish on an integrated circuit (IC) die structure or a substrate structure to which an IC die structure is to be bonded has a chemical composition distinct from that of underlying metallization. The surface finish may comprise a Cu—Ni alloy. Optionally, the Cu—Ni alloy may further comprise Mn. Alternatively, the surface finish may comprise a noble metal, such as Pd, Pt, or Ru or may comprise self-assembled monolayer (SAM) molecules comprising Si and C. During the bonding process a biphilic surface on the IC die structure or substrate structure may facilitate liquid droplet-based fine alignment of the IC die structure to a host structure. Prior to bonding, the surface finish may be applied upon a top surface of metallization features and may inhibit oxidation of the top surface exposed to the liquid droplet.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Kimin Jun, Feras Eid, Adel Elsherbini, Veronica Strong, Thomas Sounart
  • Publication number: 20250112200
    Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Kimin Jun, Feras Eid, Thomas Sounart, Yi Shi, Shawna Liff, Johanna Swan, Michael Baker, Bhaskar Jyoti Krishnatreya, Chien-An Chen
  • Publication number: 20250112186
    Abstract: A surface of at least one of an integrated circuit (IC) die structure or a substrate structure to which the IC die structure is to be bonded include a biphilic region suitable for liquid droplet confinement and droplet-based fine alignment of the IC die structure to the substrate structure. A biphilic region may include an inner region surrounded by bonding regions, or between an adjacent pair of bonding regions. The inner region may improve fine alignment, particularly if there is a significant amount of tilt between a bonding surface of the IC die structure and a bonding surface of the substrate structure during placement. The inner region may, for example, facilitate the confinement of two or more droplets on the bonding regions. Inner or outer regions of a biphilic structure may be segmented or contiguous and intersecting IC die edges may also be non-orthogonal.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Thomas Sounart, Kimin Jun, Wenhao Li
  • Publication number: 20250112199
    Abstract: Hybrid bonded multi-level die stacks, related apparatuses, systems, and methods of fabrication are disclosed. First-level integrated circuit (IC) dies and a base substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet followed by anneal. Hybrid bonding regions of second-level IC dies are similarly bonded to hybrid bonding regions on backsides of the first-level IC dies. This is repeated for any number of subsequent levels of IC dies. IC structures including the bonded IC dies and portions of the base substrate are segmented and assembled.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Thomas Sounart, Feras Eid, Adel Elsherbini, Yi Shi, Michael Baker, Kimin Jun, Wenhao Li
  • Publication number: 20250112185
    Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by superhydrophobic structures that have a contact angle not less than 150 degrees. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. The liquid droplet is pinned to the hybrid bonding regions by the superhydrophobic structures. A hybrid bond is formed by evaporating the droplet and a subsequent anneal.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Thomas Sounart, Michael Baker, Seyed Hadi Zandavi, Yi Shi, Feras Eid
  • Publication number: 20250112196
    Abstract: An embodiment discloses an electronic device, comprising an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Feras Eid, Johanna Swan, Adel Elsherbini, Thomas L. Sounart, Tushar Kanti Talukdar, Brandon M. Rawlings, Kimin Jun, Andrey Vyatskikh, Shawna M. Liff
  • Publication number: 20250112181
    Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die and a surface of a substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hydrophobic structures include non-vertical inward sloping sidewalls or similar features to contain a liquid droplet that is applied to the die or substrate hybrid bonding region. After the hybrid bonding regions are brought together, capillary forces cause the die to self-align, and a hybrid bond is formed by evaporating the liquid and subsequent anneal. IC structures including the IC die and portions of the substrate are segmented and assembled.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Feras Eid, Yi Shi, Kimin Jun, Adel Elsherbini, Thomas Sounart, Wenhao Li, Xavier Brun
  • Publication number: 20250112208
    Abstract: Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a microelectronic assembly includes a solid glass layer, a plurality of mesa structures on a surface of the glass layer, and an integrated circuit (IC) component on each respective mesa structure. The mesa structures have similar footprints as the IC components, and may be formed on or integrated with the glass layer.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Thomas L. Sounart, Feras Eid, Kimin Jun, Tushar Kanti Talukdar, Andrey Vyatskikh, Johanna Swan, Shawna M. Liff
  • Publication number: 20250112218
    Abstract: In one embodiment, a selective layer transfer process includes forming a layer of integrated circuit (IC) components on a first substrate, forming first bonding structures on a second substrate, and partially bonding the first substrate to the second substrate, which includes bonding a first subset of IC components on the first substrate to respective bonding structures on the second substrate. The process also includes forming second bonding structures on a third substrate, where the second bonding structures are arranged in a layout that is offset from the layout of the second substrate. The process further includes partially bonding the first substrate to the third substrate, which includes bonding a second subset of IC components on the first substrate to respective bonding structures on the third substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Brandon M. Rawlings, Adel Elsherbini, Thomas L. Sounart, Feras Eid, Tushar Kanti Talukdar, Kimin Jun, Johanna Swan, Richard F. Vreeland
  • Publication number: 20250112210
    Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more transistors that contain one or more group III-V materials. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Adel Elsherbini, Feras Eid, Thomas L. Sounart, Georgios C. Dogiamis, Tushar Kanti Talukdar
  • Publication number: 20250112067
    Abstract: In one embodiment, a selective transfer process includes forming a layer of integrated circuit (IC) components on a first substrate. The method also includes dispensing liquid droplets into a subset of a plurality of areas of a second substrate, where the areas of the second substrate are defined by hydrophobic lines patterned to match a layout of the IC components on the first substrate. The method further includes partially bonding the first substrate to the second substrate, where a subset of the IC components on the first substrate are bonded to the liquid droplets on the second substrate (e.g., via capillary forces), and separating the first substrate from the second substrate. When the first substrate is separated from the second substrate, the subset of IC components is separated from the first substrate and remain on the second substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Thomas L. Sounart, Feras Eid, Tushar Kanti Talukdar, Adel Elsherbini, Carlos Bedoya Arroyave, Johanna Swan
  • Publication number: 20250112187
    Abstract: A surface of an integrated circuit (IC) die structure or a host structure to which the IC die structure is to be bonded includes a biphilic surface for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. Hydrophobic regions can be self-aligned to hydrophilic regions of the biphilic surface by forming precursor metallization features within the hydrophobic regions concurrently with the formation of metallization features within the hydrophilic regions. Metallization features within the hydrophobic regions may then be at least partially removed as sacrificial to facilitate the formation of a hydrophobic surface. Metallization features within the hydrophilic regions may be retained and ultimately bonded to complementary features of another IC die structure or substrate structure.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Kimin Jun, Feras Eid, Adel Elsherbini, Thomas Sounart, YI Shi
  • Patent number: 12266682
    Abstract: Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mohammad Enamul Kabir, Zhiguo Qian, Gerald S. Pasdast, Kimin Jun, Shawna M. Liff, Johanna M. Swan, Aleksandar Aleksov, Feras Eid