Patents by Inventor Feras Eid

Feras Eid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190006282
    Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers, a cavity formed in at least one organic dielectric layer of the plurality of organic dielectric layers and a modular structure having first and second ports and a conductive member that is formed within the cavity. The conductive member provides modularity by being capable of connecting the first and second ports and also disconnecting the first and second ports.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventor: Feras EID
  • Publication number: 20190003854
    Abstract: An apparatus is provided which comprises: a substrate; a sensor including a sensing element, wherein the sensor is integrated within the substrate; and a calibration structure integrated within the substrate, wherein the calibration structure is to exhibit one or more physical or chemical properties same as the sensor but without the sensing element.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Inventors: Sasha Oster, Feras Eid, Thomas L. Sounart, Georgios C. Dogiamis
  • Patent number: 10156583
    Abstract: A method of manufacturing an accelerometer, including placing a magnet on a substrate, laminating a dielectric layer over the magnet, forming a conductive layer over the dielectric layer, the conductive layer including a mass and a conductive path overlying the magnet, removing a portion of the dielectric layer proximate the mass and conductive path such that the mass is movable in response to acceleration of the accelerometer, and forming a dielectric layer over the mass to form a space between the mass and the dielectric layer formed over the mass sufficiently clear such that the mass remains movable.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Qing Ma, Valluri Rao, Feras Eid, Kevin Lin, Weng Hong Teh, Johanna M. Swan, Robert L. Sankman
  • Patent number: 10134656
    Abstract: Embodiments include a synthetic jet device formed within layers of a package substrate, such as to provide a controlled airflow for sensing or cooling applications. The jet device includes an electromagnetically driven vibrating membrane of conductive material between a top and bottom cavity. A top lid with an opening covers the top cavity, and a permanent magnet is below the bottom cavity. An alternating current signal conducted through the membrane causes the membrane to vibrate in the presence of a magnetic field caused by the permanent magnet. By being manufactured with package forming processes, the jet (1) is manufactured more cost-effectively than by using silicon chip or wafer processing; (2) is easily integrated as part of and with the other layers of a package substrate; and (3) can be driven by a chip mounted on the package. Embodiments also include systems having and processes for forming the jet.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Feras Eid, Jessica Gullbrand, Melissa A. Cowan
  • Publication number: 20180328957
    Abstract: Embodiments of the invention include a microelectronic device having a sensing device and methods of forming the sensing device. In an embodiment, the sensing device includes a mass and a plurality of beams to suspend the mass. Each beam comprises first and second conductive layers and an insulating layer positioned between the first and second conductive layers to electrically isolate the first and second conductive layers. The first conductive layer is associated with drive signals and the second conductive layer is associated with sense signals of the sensing device.
    Type: Application
    Filed: December 17, 2015
    Publication date: November 15, 2018
    Inventors: Feras EID, Henning BRAUNISCH, Georgios C. DOGIAMIS, Sasha N. OSTER
  • Publication number: 20180331003
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Application
    Filed: December 16, 2015
    Publication date: November 15, 2018
    Inventors: Krishna BHARATH, Mathew J. MANUSHAROW, Adel A. ELSHERBINI, Mihir K. ROY, Aleksandar ALEKSOV, Yidnekachew S. MEKONNEN, Javier SOTO GONZALEZ, Feras EID, Suddhasattwa NAD, Meizi JIAO
  • Patent number: 10121730
    Abstract: Embodiments include a synthetic jet device formed within layers of a package substrate, such as to provide a controlled airflow for sensing or cooling applications. The jet device includes an electromagnetically driven vibrating membrane of conductive material between a top and bottom cavity. A top lid with an opening covers the top cavity, and a permanent magnet is below the bottom cavity. An alternating current signal conducted through the membrane causes the membrane to vibrate in the presence of a magnetic field caused by the permanent magnet. By being manufactured with package forming processes, the jet (1) is manufactured more cost-effectively than by using silicon chip or wafer processing; (2) is easily integrated as part of and with the other layers of a package substrate; and (3) can be driven by a chip mounted on the package. Embodiments also include systems having and processes for forming the jet.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Feras Eid, Jessica Gullbrand, Melissa A. Cowan
  • Publication number: 20180315690
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 1, 2018
    Inventors: Adel A. ELSHERBINI, Mathew J. MANUSHAROW, Krishna BHARATH, William J. LAMBERT, Robert L. SANKMAN, Aleksandar ALEKSOV, Brandon M. RAWLINGS, Feras EID, Javier SOTO GONZALEZ, Meizi JIAO, Suddhasattwa NAD, Telesphor KAMGAING
  • Patent number: 10116504
    Abstract: Embodiments of the invention include a physiological sensor system. According to an embodiment the sensor system may include a package substrate, a plurality of sensors formed on the substrate, a second electrical component, and an encryption bank formed along a data transmission path between the plurality of sensors and the second electrical component. In an embodiment the encryption bank may include a plurality of portions that each have one or more switches integrated into the package substrate. In an embodiment each sensor transmits data to the second electrical component along different portions of the encryption bank. In some embodiments, the switches may be piezoelectrically actuated. In other embodiments the switches may be actuated by thermal expansion. Additional embodiments may include tri- or bi-stable mechanical switches.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Sasha N. Oster, Feras Eid, Georgios C. Dogiamis, Thomas L. Sounart, Johanna M. Swan
  • Publication number: 20180310399
    Abstract: Embodiments of the invention include a waveguide structure that includes a lower member, at least one sidewall member coupled to the lower member, and an upper member. The lower member, the at least one sidewall member, and the upper member include at least one conductive layer to form a cavity in a substrate for allowing communications between devices that are coupled or attached to the substrate.
    Type: Application
    Filed: December 21, 2015
    Publication date: October 25, 2018
    Inventors: Vijay K. NAIR, Sasha N. OSTER, Adel A. ELSHERBINI, Telesphor KAMGAING, Feras EID
  • Publication number: 20180287115
    Abstract: An apparatus system is provided which comprises: a fabric; a self-assembled monolayer (SAM) material formed on the fabric; and a battery cell formed on the fabric, wherein a current collector of the battery cell is at least in part formed on the SAM material.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Veronica A. Strong, Sasha N. Oster, Feras Eid, Aranzazu Maestre Caro
  • Publication number: 20180288868
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 4, 2018
    Inventors: Adel A. ELSHERBINI, Matthew MANUSHAROW, Krishna BHARATH, Zhichao ZHANG, Yidnekachew S. MEKONNEN, Aleksandar ALEKSOV, Henning BRAUNISCH, Feras EID, Javier SOTO
  • Patent number: 10083923
    Abstract: Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the packaged device may include an integrated circuit chip mounted to a package substrate. According to an embodiment, the package substrate may have conductive lines that communicatively couple the integrated circuit chip to one or more external components. One of the external components may be an RFIC module. The RFIC module may comprise an RFIC and an antenna. Additional embodiments may also include a packaged device that includes a plurality of cooling spots formed into the package substrate. In an embodiment the cooling spots may be formed proximate to interconnect lines the communicatively couple the integrated circuit chip to the RFIC.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Georgios C. Dogiamis, Sasha N. Oster, Telesphor Kamgaing, Adel A. Elsherbini, Brandon M. Rawlings, Feras Eid
  • Publication number: 20180263117
    Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.
    Type: Application
    Filed: November 13, 2017
    Publication date: September 13, 2018
    Inventors: Sasha N. Oster, Robert L. Sankman, Charles Gealer, Omkar Karhade, John S. Guzek, Ravindranath V. Mahajan, James C. Matayabas, JR., Johanna M. Swan, Feras Eid, Shawna Liff, Timothy McIntosh, Telesphor Kamgaing, Adel A. Elsherbini, Kemal Aygun
  • Patent number: 10068852
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: September 4, 2018
    Assignee: INTEL CORPORATION
    Inventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
  • Publication number: 20180233431
    Abstract: Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 16, 2018
    Inventors: Adel A. ELSHERBINI, Henning BRAUNISCH, Brandon M. RAWLINGS, Aleksandar ALEKSOV, Feras EID, Javier SOTO
  • Publication number: 20180226310
    Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 9, 2018
    Inventors: Feras EID, Adel A. ELSHERBINI, Henning BRAUNISCH, Yidnekachew MEKONNEN, Krishna BHARATH, Mathew J. MANUSHAROW, Aleksandar ALEKSOV, Nathan FRITZ
  • Patent number: 10039186
    Abstract: A circuit interconnect may be used in biometric data sensing and feedback applications. A circuit interconnect may be used in device device-to-device connections (e.g., Internet of Things (IoT) devices), including applications that require connection between stretchable and rigid substrates. A circuit interconnect may include a multi-pin, snap-fit attachment mechanism, where the attachment mechanism provides an electrical interconnection between a rigid substrate and a flexible or stretchable substrate. The combination of a circuit interconnect and flexible or stretchable substrate provides improved electrical connection reliability, allows for greater stretchability and flexibility of the circuit traces, and allows for more options in connecting a stretchable circuit trace to a rigid PCB.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: July 31, 2018
    Assignee: Intel Corporation
    Inventors: Amit Sudhir Baxi, Vincent S. Mageshkumar, Adel A. Elsherbini, Sasha Oster, Feras Eid, Aleksandar Aleksov, Johanna M. Swan
  • Patent number: 10032052
    Abstract: Embodiments of the invention include delay line circuitry that is integrated with an organic substrate. Organic dielectric material and a plurality of conductive layers form the organic substrate. The delay line circuitry includes a piezoelectric transducer to receive a guided electromagnetic wave signal and to generate an acoustic wave signal to be transmitted with an acoustic transmission medium. An acoustic reflector is communicatively coupled to the acoustic transmission medium. The acoustic reflector receives a plurality of acoustic wave signals from the acoustic transmission medium and reflects acoustic wave signals to the piezoelectric transducer using the acoustic transmission medium. The transducer converts the reflected acoustic signals into electromagnetic waves which are then transmitted back through the antenna and decoded by the reader.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Telesphor Kamgaing, Feras Eid, Vijay K. Nair, Georgios C. Dogiamis, Johanna M. Swan, Valluri R. Rao
  • Publication number: 20180182736
    Abstract: An embodiment includes an apparatus comprising: a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (W/(m·K)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity. Other embodiments are described herein.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Feras Eid, Nader N. Abazarnia, Johanna M. Swan, Taesha D. Beasley, Sasha N. Oster, Tannaz Harirchian, Shawna M. Liff