Patents by Inventor Feras Eid

Feras Eid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ACTIVE VENTING GARMENT USING PIEZOELECTRIC ELEMENTS
    Publication number: 20190297975
    Abstract: Embodiments of the invention include an active venting system. According to an embodiment of the invention, the active venting system may include a substrate having one or more seams formed through the substrate. In order to open the vents defined by the seams through the substrate, a piezoelectric layer may be formed proximate to one or more of the seams. Additional embodiments may include a first electrode and a second electrode that contact the piezoelectric layer in order to provide a voltage differential across the piezoelectric layer. In an embodiment the active venting system may be integrated into a garment. In such an embodiment, the garment may also include an electronics module for controlling the actuators. Additionally, conductive traces may be printed on the garment or sewn into the garment to provide electrical connections from the electronics module to each of the piezoelectric actuators.
    Type: Application
    Filed: July 2, 2016
    Publication date: October 3, 2019
    Inventors: Aleksandar ALEKSOV, Sasha N. OSTER, Feras EID, Shawna M. LIFF, Thomas L. SOUNART, Johanna M. SWAN, Baris BICEN, Valluri R. RAO
  • Piezoelectric package-integrated crystal devices
    Patent number: 10432167
    Abstract: Embodiments of the invention include a piezoelectric resonator which includes an input transducer having a first piezoelectric material, a vibrating structure coupled to the input transducer, and an output transducer coupled to the vibrating structure. In one example, the vibrating structure is positioned above a cavity of an organic substrate. The output transducer includes a second piezoelectric material. In operation the input transducer causes an input electrical signal to be converted into mechanical vibrations which propagate across the vibrating structure to the output transducer.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Feras Eid, Baris Bicen, Telesphor Kamgaing, Vijay K. Nair, Johanna M. Swan, Georgios C. Dogiamis, Valluri R. Rao
  • Thermal management of molded packages
    Patent number: 10424559
    Abstract: An embodiment includes an apparatus comprising: a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (W/(m·K)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity. Other embodiments are described herein.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Nader N. Abazarnia, Johanna M. Swan, Taesha D. Beasley, Sasha N. Oster, Tannaz Harirchian, Shawna M. Liff
  • Embedded formation of wearable and flexible batteries
    Patent number: 10418605
    Abstract: An apparatus system is provided which comprises: a fabric; a self-assembled monolayer (SAM) material formed on the fabric; and a battery cell formed on the fabric, wherein a current collector of the battery cell is at least in part formed on the SAM material.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Veronica A. Strong, Sasha N. Oster, Feras Eid, Aranzazu Maestre Caro
  • Package power delivery using plane and shaped vias
    Patent number: 10410939
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
  • Integrated sensor and homologous calibration structure for resonant devices
    Patent number: 10386204
    Abstract: An apparatus is provided which comprises: a substrate; a sensor including a sensing element, wherein the sensor is integrated within the substrate; and a calibration structure integrated within the substrate, wherein the calibration structure is to exhibit one or more physical or chemical properties same as the sensor but without the sensing element.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Sasha Oster, Feras Eid, Thomas L. Sounart, Georgios C. Dogiamis
  • PIEZOELECTRIC DEVICES FABRICATED IN PACKAGING BUILD-UP LAYERS
    Publication number: 20190252597
    Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Feras EID, Shawna M. LIFF
  • Lithographacally defined vias for organic package substrate scaling
    Patent number: 10381291
    Abstract: Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Henning Braunisch, Brandon M. Rawlings, Aleksandar Aleksov, Feras Eid, Javier Soto
  • Dual-sided die packages
    Patent number: 10361142
    Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Feras Eid, Adel A. Elsherbini, Johanna M. Swan, Don W. Nelson
  • STACKED DIE ARCHITECTURES WITH IMPROVED THERMAL MANAGEMENT
    Publication number: 20190214328
    Abstract: A semiconductor device that has a semiconductor die coupled to a substrate. A mold compound encapsulates the semiconductor die, and at least one thermal conductive material section extends from adjacent the semiconductor die through the mold compound. The at least one conductive material section thus conveys heat from the semiconductor die through the mold compound.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Inventors: Feras Eid, Shrenik Kothari, Chandra M. Jha, Johanna M. Swan, Michael J. Baker, Shawna M. Liff, Thomas L. Sounart, Betsegaw K. Gebrehiwot, Shankar Devasenathipathy, Taylor Gaines, Digvijay Ashokkumar Raorane
  • SEMICONDUCTOR PACKAGE HAVING INTEGRATED STIFFENER REGION
    Publication number: 20190214338
    Abstract: Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.
    Type: Application
    Filed: September 14, 2016
    Publication date: July 11, 2019
    Inventors: Eng Huat GOH, Jiun Hann SIR, Min Suet LIM, Shawna M. LIFF, Feras EID
  • Microelectronic bond pads having integrated spring structures
    Patent number: 10325860
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • PACKAGE SUBSTRATE INTEGRATED DEVICES
    Publication number: 20190169020
    Abstract: A package substrate is provided which comprises: one or more first conductive contacts on a first surface; one or more second conductive contacts on a second surface opposite the first surface; a dielectric layer between the first and the second surfaces; and an embedded sensing or actuating element on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded sensing or actuating element comprises a fixed metal layer in the dielectric layer and a flexible metal layer suspended over the fixed metal layer by one or more metal supports on the dielectric layer. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 6, 2019
    Applicant: Intel Corporation
    Inventors: Aleksandar ALEKSOV, Kristof DARMAWIKARTA, Robert A. MAY, Changhua LIU, Hiroki TANAKA, Feras EID
  • Package assembly with hermetic cavity
    Patent number: 10314171
    Abstract: Apparatuses, systems and methods associated with hermetic encapsulation for package assemblies are disclosed herein. In embodiments, a package assembly may include a package substrate that includes a guard ring, wherein the guard ring extends from a surface of the package substrate and around a circumference of a cavity. The package assembly may further include a component coupled to the guard ring by a solder joint along an entirety of the guard ring, wherein the cavity is located between the package substrate and the component and the cavity is hermetically-sealed via the guard ring and the solder joint. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Johanna M. Swan
  • PIEZOELECTRIC PACKAGE-INTEGRATED PRESSURE SENSING DEVICES
    Publication number: 20190165250
    Abstract: Embodiments of the invention include a pressure sensing device having a membrane that is positioned in proximity to a cavity of an organic substrate, a piezoelectric material positioned in proximity to the membrane, and an electrode in contact with the piezoelectric material. The membrane deflects in response to a change in ambient pressure and this deflection causes a voltage to be generated in the piezoelectric material with this voltage being proportional to the change in ambient pressure.
    Type: Application
    Filed: July 1, 2016
    Publication date: May 30, 2019
    Inventors: Thomas L. SOUNART, Feras EID, Sasha N. OSTER, Georgios C. DOGIAMIS, Adel A. ELSHERBINI, Shawna M. LIFF, Johanna M. SWAN
  • Piezoelectric devices fabricated in packaging build-up layers
    Patent number: 10305019
    Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Shawna M. Liff
  • MICROELECTRONIC BOND PADS HAVING INTEGRATED SPRING STRUCTURES
    Publication number: 20190148311
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Applicant: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Tunable radio frequency systems using piezoelectric package-integrated switching devices
    Patent number: 10291283
    Abstract: Embodiments of the invention include a tunable radio frequency (RF) communication module that includes a transmitting component having at least one tunable component and a receiving component having at least one tunable component. The tunable RF communication module includes at least one piezoelectric switching device coupled to at least one of the transmitting and receiving components. The at least one piezoelectric switching device is formed within an organic substrate having organic material and is designed to tune at least one tunable component of the tunable RF communication module.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Feras Eid, Adel A. Elsherbini, Georgios C. Dogiamis, Vijay K. Nair, Johanna M. Swan, Valluri R. Rao
  • PIEZOELECTRIC PACKAGE-INTEGRATED ACOUSTIC TRANSDUCER DEVICES
    Publication number: 20190141456
    Abstract: Embodiments of the invention include an acoustic transducer device having a base structure that is positioned in proximity to a cavity of an organic substrate, a piezoelectric material in contact with a first electrode of the base structure, and a second electrode in contact with the piezoelectric material. In one example, for a transmit mode, a voltage signal is applied between the first and second electrodes and this causes a stress in the piezoelectric material which causes a stack that is formed with the first electrode, the piezoelectric material, and the second electrode to vibrate and hence the base structure to vibrate and generate acoustic waves.
    Type: Application
    Filed: July 1, 2016
    Publication date: May 9, 2019
    Inventors: Georgios C. DOGIAMIS, Feras EID, Adel A. ELSHERBINI, Johanna SWAN, Shawna M. LIFF, Thomas L. SOUNART, Sasha N. OSTER
  • PIEZOELECTRIC DEVICES FABRICATED IN PACKAGING BUILD-UP LAYERS
    Publication number: 20190140158
    Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.
    Type: Application
    Filed: March 28, 2014
    Publication date: May 9, 2019
    Inventors: Feras Eid, Shawna M. Liff