Patents by Inventor Fethi Dhaoui
Fethi Dhaoui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220262434Abstract: A ReRAM memory array includes ReRAM memory cells and a select circuit having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.Type: ApplicationFiled: May 4, 2022Publication date: August 18, 2022Applicant: Microchip Technology Inc.Inventors: Victor Nguyen, Fethi Dhaoui, John L. McCollum, Fengliang Xue
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Patent number: 11355187Abstract: A method for erasing a ReRAM memory cell that includes a ReRAM device having a select circuit with two series-connected select transistors. The method includes determining if the ReRAM cell is selected for erasing. If the ReRAM cell is selected for erasing, the bit line node is biased at a first voltage potential, the source line node is biased at a second voltage potential greater than the first voltage potential and the gates of the series-connected select transistors are supplied with positive voltage pulses. The difference between the first voltage potential and the second voltage potential is sufficient to erase the ReRAM device in the ReRAM cell. If the ReRAM cell is unselected for erasing, the gate of the one of the series-connected select transistors having its drain connected to an electrode of the ReRAM device is supplied with a voltage potential insufficient to turn it on.Type: GrantFiled: January 2, 2021Date of Patent: June 7, 2022Assignee: Microchip Technology Inc.Inventors: Victor Nguyen, Fethi Dhaoui, John L McCollum, Fengliang Xue
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Patent number: 11114348Abstract: An integrated circuit includes a plurality of low-voltage FinFET transistors each having a channel length l and a channel width w, the low-voltage FinFET transistors having a first threshold voltage channel implant and a first gate dielectric thickness. The integrated circuit also includes a plurality of high-voltage FinFET transistors each having the channel length l and the channel width w, the high-voltage FinFET transistors having a second threshold voltage channel implant greater than the first threshold voltage channel implant and second gate dielectric thickness greater than the first gate dielectric thickness.Type: GrantFiled: November 1, 2018Date of Patent: September 7, 2021Assignee: Microsemi SoC Corp.Inventors: John McCollum, Fethi Dhaoui, Pavan Singaraju
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Patent number: 11031078Abstract: A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.Type: GrantFiled: March 25, 2019Date of Patent: June 8, 2021Assignee: Microsemi SoC Corp.Inventors: Fengliang Xue, Fethi Dhaoui, Pavan Singaraju, Victor Nguyen, John L. McCollum, Volker Hecht
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Publication number: 20210125666Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.Type: ApplicationFiled: January 2, 2021Publication date: April 29, 2021Applicant: Microchip Technology Inc.Inventors: Victor Nguyen, Fethi Dhaoui, John L McCollum, Fengliang Xue
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Patent number: 10910050Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.Type: GrantFiled: May 7, 2019Date of Patent: February 2, 2021Assignee: Microchip Technology Inc.Inventors: Victor Nguyen, Fethi Dhaoui, John L. McCollum, Fengliang Xue
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Patent number: 10872661Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.Type: GrantFiled: May 7, 2019Date of Patent: December 22, 2020Assignee: Microchip Technology Inc.Inventors: Fengliang Xue, Fethi Dhaoui, Victor Nguyen, John L. McCollum
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Publication number: 20200327937Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.Type: ApplicationFiled: May 7, 2019Publication date: October 15, 2020Applicant: Microchip Technology Inc.Inventors: Victor Nguyen, Fethi Dhaoui, John L. McCollum, Fengliang Xue
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Publication number: 20200327938Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.Type: ApplicationFiled: May 7, 2019Publication date: October 15, 2020Applicant: Microchip Technology Inc.Inventors: Fengliang Xue, Fethi Dhaoui, Victor Nguyen, John L. McCollum
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Publication number: 20200286559Abstract: A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.Type: ApplicationFiled: March 25, 2019Publication date: September 10, 2020Applicant: Microsemi SoC Corp.Inventors: Fengliang Xue, Fethi Dhaoui, Pavan Singaraju, Victor Nguyen, John L. McCollum, Volker Hecht
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Publication number: 20190172756Abstract: An integrated circuit includes a plurality of low-voltage FinFET transistors each having a channel length l and a channel width w, the low-voltage FinFET transistors having a first threshold voltage channel implant and a first gate dielectric thickness. The integrated circuit also includes a plurality of high-voltage FinFET transistors each having the channel length l and the channel width w, the high-voltage FinFET transistors having a second threshold voltage channel implant greater than the first threshold voltage channel implant and second gate dielectric thickness greater than the first gate dielectric thickness.Type: ApplicationFiled: November 1, 2018Publication date: June 6, 2019Applicant: Microsemi SoC Corp.Inventors: John McCollum, Fethi Dhaoui, Pavan Singaraju
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Patent number: 9859289Abstract: A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel. In at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extends from the drain into the channel.Type: GrantFiled: February 11, 2016Date of Patent: January 2, 2018Inventors: Fethi Dhaoui, John McCollum
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Patent number: 9755072Abstract: A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.Type: GrantFiled: March 21, 2016Date of Patent: September 5, 2017Assignee: MICROSEMI SoC CORPORATIONInventors: Fengliang Xue, Fethi Dhaoui, John L. McCollum
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Patent number: 9754948Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.Type: GrantFiled: January 15, 2014Date of Patent: September 5, 2017Assignee: MICROSEMI SoC CORPORATIONInventors: Fethi Dhaoui, John McCollum, Frank Hawley, Leslie Richard Wilkinson
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Publication number: 20170179382Abstract: A resistive random access memory device is formed in an integrated circuit between a first metal layer and a second metal layer and includes a first barrier layer disposed over the first metal layer, a tunneling dielectric layer disposed over the first barrier layer, a solid electrolyte layer disposed over the tunneling dielectric layer, an ion source layer disposed over the solid electrolyte layer, and a second barrier layer disposed over the ion source layer.Type: ApplicationFiled: December 9, 2016Publication date: June 22, 2017Applicant: Microsemi SoC CorporationInventors: John L. McCollum, Fethi Dhaoui, Frank W. Hawley
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Patent number: 9520448Abstract: A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.Type: GrantFiled: August 10, 2016Date of Patent: December 13, 2016Assignee: Microsemi SoC CorporationInventors: John L. McCollum, Fethi Dhaoui
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Publication number: 20160351626Abstract: A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.Type: ApplicationFiled: August 10, 2016Publication date: December 1, 2016Applicant: Microsemi SoC CorporationInventors: John L. McCollum, Fethi Dhaoui
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Publication number: 20160269031Abstract: A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.Type: ApplicationFiled: January 29, 2016Publication date: September 15, 2016Applicant: Microsemi SoC CorporationInventors: John L. McCollum, Fethi Dhaoui
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Patent number: 9444464Abstract: A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.Type: GrantFiled: January 29, 2016Date of Patent: September 13, 2016Assignee: Microsemi SoC CorporationInventors: John L. McCollum, Fethi Dhaoui
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Publication number: 20160204223Abstract: A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.Type: ApplicationFiled: March 21, 2016Publication date: July 14, 2016Applicant: Microsemi SoC CorporationInventors: Fengliang Xue, Fethi Dhaoui, John L. McCollum