Patents by Inventor Fethi Dhaoui
Fethi Dhaoui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7915665Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: April 2, 2009Date of Patent: March 29, 2011Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
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Patent number: 7906805Abstract: An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.Type: GrantFiled: August 22, 2008Date of Patent: March 15, 2011Assignee: Actel CorporationInventors: Michael Sadd, Fethi Dhaoui, John McCollum, Richard Chan
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Patent number: 7898018Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: January 26, 2009Date of Patent: March 1, 2011Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang
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Publication number: 20110024821Abstract: A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.Type: ApplicationFiled: October 13, 2010Publication date: February 3, 2011Inventors: Zhigang Wang, Fethi Dhaoui, Michael Sadd, John McCollum, Frank Hawley
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Publication number: 20110018070Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.Type: ApplicationFiled: September 30, 2010Publication date: January 27, 2011Inventors: Fethi Dhaoui, John McCollum, Frank Hawley, Leslie Richard Wilkinson
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Patent number: 7839681Abstract: A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.Type: GrantFiled: December 12, 2008Date of Patent: November 23, 2010Assignee: Actel CorporationInventors: Zhigang Wang, Fethi Dhaoui, Michael Sadd, John McCollum, Frank Hawley
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Patent number: 7838944Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.Type: GrantFiled: March 25, 2008Date of Patent: November 23, 2010Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Frank Hawley, Leslie Wilkinson
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Publication number: 20100208520Abstract: A push-pull non-volatile memory array includes memory cells with an n-channel non-volatile pull-down transistor in series with a p-channel volatile pull-up transistor. A non-volatile transistor row line is associated with each row of the array and is coupled to the control gates of each n-channel non-volatile pull-down transistor in the row. A volatile transistor row line is associated with each row of the array and is coupled to the control gates of each p-channel volatile pull-up transistor in the row with which it is associated. A column line is associated with each column in the array and is coupled to the source of each p-channel volatile pull-up transistor in the column with which it is associated.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Inventors: Zhigang Wang, Fethi Dhaoui, John McCollum, Vidyadhara Bellippady
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Patent number: 7768317Abstract: A radiation-tolerant flash-based FPGA switching element includes a plurality of memory cells each having a memory transistor and a switch transistor sharing a floating gate. Four such memory cells are combined such that two sets of two switch transistors are wired in series and the two sets of series-wired switch transistors are also wired in parallel. The four memory transistors associated with the series-parallel combination of switch transistors are all programmed to the same on or off state. The series combination prevents an “on” radiation-hit fault to one of the floating gates from creating a false connection and the parallel combination prevents an “off” radiation-hit fault to one of the floating gates from creating a false open circuit.Type: GrantFiled: May 21, 2008Date of Patent: August 3, 2010Assignee: Actel CorporationInventors: Fethi Dhaoui, Zhigang Wang, John McCollum, Richard Chan, Vidyadhara Bellippady
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Publication number: 20100149873Abstract: A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.Type: ApplicationFiled: December 12, 2008Publication date: June 17, 2010Applicant: ACTEL CORPORATIONInventors: Zhigang Wang, Fethi Dhaoui, Michael Sadd, John McCollum, Frank Hawley
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Patent number: 7697330Abstract: A non-volatile memory array for an FPGA comprises a plurality of memory cells arranged in rows and columns and divided into a plurality of row segments. The source of each non-volatile memory transistor in each segment is coupled together to a common source line. A column segment line is associated with each segment of the array, and is coupled to the drains of each non-volatile memory transistor in the segment. A segment select transistor is coupled between each column segment line and its associated column line, and a high-voltage driver transistor is coupled to each column line.Type: GrantFiled: December 20, 2007Date of Patent: April 13, 2010Assignee: Actel CorporationInventors: Vidyahara Bellippady, Santosh Yachareni, Fethi Dhaoui, Zhigang Wang
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Patent number: 7692972Abstract: A split-gate memory cell, includes an n-channel split-gate non-volatile memory transistor having a source, a drain, a select gate over a thin oxide, and a control gate over a non-volatile gate material and separated from the select gate by a gap. A p-channel pull-up transistor has a drain coupled to the drain of the split-gate non-volatile memory transistor, a source coupled to a bit line, and a gate. A switch transistor has first and second source/drain diffusions, and a gate coupled to the drains of the split-gate non-volatile memory transistor and the p-channel pull-up transistor. An inverter has an input coupled to the second source/drain diffusion of the switch transistor, and an output. A p-channel level-restoring transistor has a source coupled to a supply potential, a drain coupled to the first source/drain diffusion of the switch transistor and a gate coupled to the output of the inverter.Type: GrantFiled: July 22, 2008Date of Patent: April 6, 2010Assignee: Actel CorporationInventors: Michael Sadd, Fethi Dhaoui, George Wang, John McCollum
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Publication number: 20100044768Abstract: An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.Type: ApplicationFiled: August 22, 2008Publication date: February 25, 2010Inventors: Michael Sadd, Fethi Dhaoui, John McCollum, Richard Chan
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Publication number: 20100038697Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: ApplicationFiled: February 13, 2009Publication date: February 18, 2010Applicant: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
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Publication number: 20090212343Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: ApplicationFiled: April 2, 2009Publication date: August 27, 2009Applicant: ACTEL CORPORATIONInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
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Patent number: 7573093Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: October 29, 2007Date of Patent: August 11, 2009Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
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Publication number: 20090159954Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: ApplicationFiled: January 26, 2009Publication date: June 25, 2009Applicant: ACTEL CORPORATIONInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang
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Patent number: 7548095Abstract: An isolation scheme to permit partial programming of FPGA integrated circuits controlled by Flash memory cells includes a p-type semiconductor region. First and second spaced apart deep n-wells are disposed in the p-type semiconductor region. First and second p-wells are respectively disposed in the first and second deep n-wells. First and second segments of Flash memory are disposed in the in first and second p-wells. N-type regions are disposed in each deep n-well between the outer boundary of the p-wells and the outer boundary of the deep n-wells.Type: GrantFiled: January 30, 2008Date of Patent: June 16, 2009Assignee: Actel CorporationInventors: Zhigang Wang, Fethi Dhaoui, Santosh Yachareni
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Patent number: 7538379Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: December 16, 2005Date of Patent: May 26, 2009Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
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Patent number: 7538382Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: October 29, 2007Date of Patent: May 26, 2009Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang