Patents by Inventor Flavio Villa

Flavio Villa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4682197
    Abstract: This integrated semiconductor device aims at drastic reduction of the direct secondary breakdown phenomena and has a plurality of side-by-side elementary transistors forming an interdigited structure. To reduce the thermal interaction between the elementary transistors, the latter are spaced apart from one another by a distance approximately equal to the width of one elementary transistor and are driven by current sources. Spacing apart reduces electrothermal interaction. Further, in order to minimize the device area requirements, the space between any two adjacent elementary transistors is made to accommodate drive transistors operating as current sources, or the elementary transistors of the complementary stage where the device forms a class B output stage, the two output transistors whereof are alternatively switched on.
    Type: Grant
    Filed: December 23, 1985
    Date of Patent: July 21, 1987
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Flavio Villa, Bruno Murari, Franco Bertotti, Aldo Torazzina, Fabrizio Stefani
  • Patent number: 4672235
    Abstract: A power transistor comprising a plurality of elementary transistors coupled in parallel and an identical number of current generators, each of which has a terminal coupled individually to the base of an elementary transistor is described. High power levels may be achieved with a transistor of this type without forward secondary breakdown taking place.
    Type: Grant
    Filed: May 21, 1985
    Date of Patent: June 9, 1987
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Flavio Villa, Bruno Murari, Carlo Cini, Franco Bertotti
  • Patent number: 4663647
    Abstract: A buried-resistance semiconductor device is constructed by forming a P-type monocrystalline silicon substrate on which an epitaxial layer of silicon doped with type N impurities is grown, a portion of the epitaxial layer being insulated by a P-type insulating region extending from the substrate to the surface of the epitaxial layer. Two suitably-spaced terminals are secured to the surface of the epitaxial layer in the area bounded by the insulating region. Two separation regions extending into the surface layer are formed in the part of the epitaxial layer between the terminals, and a buried region extends from the substrate between the separation regions without being in contact with them. The three regions are of P-type material, and have an elongated shape and are bounded at the ends by the insulating region.
    Type: Grant
    Filed: September 23, 1985
    Date of Patent: May 5, 1987
    Assignee: SGS Microelettronica SpA
    Inventors: Franco Bertotti, Paolo Ferrari, Luigi Silvestri, Flavio Villa