Patents by Inventor Flavio Villa

Flavio Villa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8334188
    Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: December 18, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Patent number: 7906321
    Abstract: An integrated semiconductor chemical microreactor for real-time polymerase chain reaction (PCR) monitoring, has a monolithic body of semiconductor material; a number of buried channels formed in the monolithic body; an inlet trench and an outlet trench for each buried channel; and a monitoring trench for each buried channel, extending between the inlet and outlet trenches thereof from the top surface of the monolithic body to the respective buried channel. Real-time PCR monitoring is carried out by channeling light beams into the buried channels, possibly through one of the inlet or outlet trenches, whereby the light beams impinge on the fluid therein and collecting the emergent light coming out from the monitoring trench.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: March 15, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ubaldo Mastromatteo, Flavio Villa, Gabriele Barlocchi
  • Publication number: 20100237459
    Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
    Type: Application
    Filed: June 1, 2010
    Publication date: September 23, 2010
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Flavio VILLA, Gabriele Barlocchi, Pietro Corona
  • Patent number: 7754578
    Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: July 13, 2010
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Patent number: 7705416
    Abstract: A method of forming buried cavities in a wafer of monocrystalline semiconductor material with at least one cavity formed in a substrate of monocrystalline semiconductor material by timed TMAH etching silicon; covering the cavity with a material inhibiting epitaxial growth; and growing a monocrystalline epitaxial layer above the substrate and the cavities. Thereby, the cavity is completely surrounded by monocrystalline material. Starting from this wafer, it is possible to form a thin membrane. The original wafer must have a plurality of elongate cavities or channels, parallel and adjacent to one another. Trenches are then excavated in the epitaxial layer as far as the channels, and the dividers between the channels are removed by timed TMAH etching.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: April 27, 2010
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gabriele Barlocchi, Flavio Villa
  • Patent number: 7452713
    Abstract: A process for manufacturing a microfluidic device, including the steps of: forming at least one channel in a semiconductor material body; forming a dielectric diaphragm above the channel, for closing the channel; and forming heating elements for providing thermal energy inside the channel. The heating elements are formed directly on said dielectric diaphragm.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: November 18, 2008
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gabriele Barlocchi, Pietro Corona, Ubaldo Mastromatteo, Flavio Villa
  • Publication number: 20080036030
    Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
    Type: Application
    Filed: September 28, 2007
    Publication date: February 14, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Patent number: 7294536
    Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: November 13, 2007
    Assignee: STMicroelectronics S.R.L.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Publication number: 20070252224
    Abstract: The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by a semiconductor layer completely encircling mask portions of insulating material.
    Type: Application
    Filed: May 1, 2007
    Publication date: November 1, 2007
    Applicant: STMicroelectronics S.r.l.
    Inventors: Gabriele Barlocchi, Ubaldo Mastromatteo, Flavio Villa
  • Publication number: 20070155183
    Abstract: To manufacture a layer of semiconductor material, a first wafer of semiconductor material is subjected to implantation to form a defect layer at a distance from a first face; the first wafer is bonded to a second wafer, by putting an insulating layer present on the second wafer in contact with the first face of the first wafer. Then, hydrogen atoms are introduced into the first wafer through a second face at an energy such as to avoid defects to be generated in the first wafer and at a temperature lower than 600° C. Thereby, the first wafer splits into a usable layer, bonded to the second wafer, and a remaining layer disposed between the defect layer and the second face of the first wafer. Prior to bonding, the first wafer is subjected to processing steps for obtaining integrated components.
    Type: Application
    Filed: December 1, 2006
    Publication date: July 5, 2007
    Applicant: STMicroelectronics S.R.L.
    Inventors: Giampiero Ottaviani, Federico Corni, Paolo Ferrari, Flavio Villa
  • Publication number: 20070126071
    Abstract: A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front face and delimiting, with the front face, a surface region of the monolithic body, said surface region having a first thickness; carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body towards the surface region and thus form a suspended structure above the buried cavity, the suspended structure having a second thickness greater than the first thickness. The thickening thermal treatment is an annealing treatment.
    Type: Application
    Filed: September 27, 2006
    Publication date: June 7, 2007
    Inventors: Pietro Corona, Flavio Villa, Gabriele Barlocchi
  • Publication number: 20070057355
    Abstract: A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the presence of a deoxidizing atmosphere so as to englobe the deoxidizing atmosphere within the trenches; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and to form a buried cavity. Furthermore, before the thermal treatment is carried out, a barrier layer that is substantially impermeable to hydrogen is formed on the closing layer on top of the trenches.
    Type: Application
    Filed: July 12, 2006
    Publication date: March 15, 2007
    Inventors: Gabriele Barlocchi, Pietro Corona, Dino Faralli, Flavio Villa
  • Publication number: 20070042558
    Abstract: In a process for manufacturing a SOI wafer, the following steps are envisaged: forming, in a monolithic body of semiconductor material having a front face, a buried cavity, which extends at a distance from the front face and delimits, with the front face, a surface region of the monolithic body, the surface region being surrounded by a bulk region and forming a flexible membrane suspended above the buried cavity; forming, through the monolithic body, at least one access passage, which reaches the buried cavity; and filling the buried cavity uniformly with an insulating region. The surface region is continuous and formed by a single portion of semiconductor material, and the buried cavity is contained and completely insulated within the monolithic body; the step of forming at least one access passage is performed after the step of forming a buried cavity.
    Type: Application
    Filed: June 6, 2006
    Publication date: February 22, 2007
    Inventors: Flavio Villa, Pietro Corona, Gabriele Barlocchi
  • Publication number: 20060260408
    Abstract: A process for manufacturing an integrated differential pressure sensor includes forming, in a monolithic body of semiconductor material having a first face and a second face, a cavity extending at a distance from the first face and delimiting therewith a flexible membrane, forming an access passage in fluid communication with the cavity, and forming, in the flexible membrane, at least one transduction element configured so as to convert a deformation of the flexible membrane into electrical signals. The cavity is formed in a position set at a distance from the second face and delimits, together with the second face, a portion of the monolithic body. In order to form the access passage, the monolithic body is etched so as to form an access trench extending through it.
    Type: Application
    Filed: May 4, 2006
    Publication date: November 23, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Flavio Villa, Pietro Corona, Gabriele Barlocchi, Lorenzo Baldo
  • Publication number: 20060185428
    Abstract: A manufacturing process of a semiconductor piezoresistive accelerometer includes the steps of: providing a wafer of semiconductor material; providing a membrane in the wafer over a cavity; rigidly coupling an inertial mass to the membrane; and providing, in the wafer, piezoresistive transduction elements, that are sensitive to strains of the membrane and generate corresponding electrical signals. The step of coupling is carried out by forming the inertial mass on top of a surface of the membrane opposite to the cavity. The accelerometer is advantageously used in a device for monitoring the pressure of a tire of a vehicle.
    Type: Application
    Filed: January 24, 2006
    Publication date: August 24, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Chantal Combi, Lorenzo Baldo, Dino Faralli, Flavio Villa
  • Patent number: 7071073
    Abstract: For manufacturing an SOI substrate, the following steps are carried out: providing a wafer of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine cavity and laterally delimiting a plurality of pillars of semiconductor material; and oxidizing the pillars of semiconductor material to form a buried insulating layer. For forming the labyrinthine cavity, a trench is first formed in a substrate; an epitaxial layer is grown, which closes the trench at the top; the wafer is annealed so as to deform the pillars and cause them to assume a minimum-energy handlebar-like shape, and a peripheral portion of the wafer is removed to reach the labyrinthine cavity, and side inlet openings are formed in the labyrinthine cavity. Oxidation is performed by feeding an oxidizing fluid through the side inlet openings.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: July 4, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Publication number: 20060063352
    Abstract: A process manufactures a wafer using semiconductor processing techniques. A bonding layer is formed on a top surface of a first wafer; a deep trench is dug in a substrate of semiconductor material belonging to a second wafer. A top layer of semiconductor material is formed on top of the substrate so as to close the deep trench at the top and form at least one buried cavity. The top layer of the second wafer is bonded to the first wafer through the bonding layer. The two wafers are subjected to a thermal treatment that causes bonding of at least one portion of the top layer to the first wafer and widening of the buried cavity. In this way, the portion of the top layer bonded to the first wafer is separated from the rest of the second wafer, to form a composite wafer.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 23, 2006
    Applicant: STMicroelectronics S.r.I
    Inventors: Gabriele Barlocchi, Flavio Villa
  • Patent number: 7009154
    Abstract: The microreactor is completely integrated and is formed by a semiconductor body having a surface and housing at least one buried channel accessible from the surface of the semiconductor body through two trenches. A heating element extends above the surface over the channel and a resist region extends above the heating element and defines an inlet reservoir and an outlet reservoir. The reservoirs are connected to the trenches and have, in cross-section, a larger area than the trenches. The outlet reservoir has a larger area than the inlet reservoir. A sensing electrode extends above the surface and inside the outlet reservoir.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: March 7, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Flavio Villa, Ubaldo Mastromatteo, Gabriele Barlocchi, Mauro Cattaneo
  • Patent number: 6992367
    Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: January 31, 2006
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Pietro Erratico, Enrico Sacchi, Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Publication number: 20060017131
    Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
    Type: Application
    Filed: December 20, 2002
    Publication date: January 26, 2006
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona