Abstract: An array of III-V material transistors singulated from a Si or SiC wafer disposed on a stretchable tape compatible with pick and place tools and a method of forming same.

Abstract: A photonic module and a method of making same, the module having one or more optoelectronic chips, such as a laser diode typically having six sides, with each optoelectronic chip having two opposing sides (a first side and a second side) abutting and electrically connected to metal regions (preferably electro-formed), the two metal regions are physically distinct and electrically separate from each other, the two electro-formed metal regions serving, in use, as heat spreaders for conducting heat away from the optoelectronic chip.

Abstract: A method for creating at least one cavity in a semiconductor substrate including the steps of: (a) partially ablating the semiconductor substrate from the top side with a laser to form a trench in the semiconductor substrate surrounding a cross section of the semiconductor material having the desired shape, (b) machining the backside of the semiconductor substrate partially ablated in step (a) to reduce the semiconductor substrate to a final thickness that is equal to or less than the laser ablation depth to form a plug of semiconductor material unattached to a remainder of the semiconductor substrate; and (c) removing the plug of semiconductor material from the semiconductor substrate to form the at least one cavity with cross section of desired shape extending through the semiconductor substrate.

Abstract: An electronic assembly including: a wafer defining at least one cavity; a chip disposed in the cavity; and a metal heat spreader disposed in the cavity, the chip being embedded in the metal heat spreader; wherein the metal heat spreader has at least one elongate microstructure separated from a remainder of the metal heat spreader by at least one channel; wherein the metal heat spreader occupies an area within the cavity that is not occupied by the chip; and wherein the at least one elongate microstructure is configured and arranged in the cavity so as to improve thermal management of the chip by reducing stress across the chip as compared with a configuration and arrangement in which a heat spreader made of the metal and occupying the area within the cavity is a solid without channels. Also, a method for forming the electronic assembly.

Abstract: An integrated radar circuit comprising: a first substrate, of a first semiconductor material, said first substrate comprising an integrated transmit and receive radar circuit; a second substrate, of a second semiconductor material, said second substrate comprising at least on through-substrate cavity having cavity walls; at least one discrete transistor chip, of a third semiconductor material, said at least one discrete transistor chip having chip walls and being held in said at least one through-substrate cavity by a metal filling extending from at least one cavity wall to at least one chip wall; a conductor on said second substrate, electrically connecting a portion of said integrated transmit and receive radar circuit to a discrete transistor on said at least one discrete transistor chip.

Abstract: An electronic assembly comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising an integrated circuit contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by direct contact of at least a side surface of said component chip with an attachment metal that fills at least a portion of said through-wafer cavity; said component chip comprising at least one component contact pad on said component chip bottom surface; and a conductor connecting said integrated circuit contact pad and said component contact pad.

Abstract: Some variations provide a magnetically anisotropic structure comprising a hexaferrite film disposed on a substrate, wherein the hexaferrite film contains a plurality of discrete and aligned magnetic hexaferrite particles, wherein the hexaferrite film is characterized by an average film thickness from about 1 micron to about 500 microns, and wherein the hexaferrite film contains less than 2 wt % organic matter. The hexaferrite film does not require a binder. Discrete particles are not sintered or annealed together because the maximum processing temperature to fabricate the structure is 500° C. or less, such as 250° C. or less. The magnetic hexaferrite particles may contain barium hexaferrite (BaFe12O19) and/or strontium hexaferrite (SrFe12O19). The hexaferrite film may be characterized by a remanence-to-saturation magnetization ratio of at least 0.7. Methods of making and using the magnetically anisotropic structure are also described.

Abstract: Some variations provide a magnetically anisotropic structure comprising a magnetically anisotropic film on a substrate, wherein the magnetically anisotropic film contains a plurality of discrete magnetic hexaferrite particles, wherein the film is characterized by an average film thickness from 1 micron to 5 millimeters, and wherein the magnetically anisotropic film contains from 2 wt % to 75 wt % organic matter. Some variations provide a magnetically anisotropic structure comprising an out-of-plane magnetically anisotropic film on a substrate, wherein the magnetically anisotropic film contains a plurality of discrete magnetic hexaferrite particles, wherein the film is characterized by an average film thickness from 1 micron to 5 millimeters, and wherein the magnetically anisotropic film contains a concentration of hexaferrite particles of at least 40 vol %.

Abstract: A micro-optical bench includes a substrate having a multi-layer trench and a micro-lens aligned by and mounted to the substrate in the multi-layer trench.

Abstract: Some variations provide a magnetically anisotropic structure comprising a hexaferrite film disposed on a substrate, wherein the hexaferrite film contains a plurality of discrete and aligned magnetic hexaferrite particles, wherein the hexaferrite film is characterized by an average film thickness from about 1 micron to about 500 microns, and wherein the hexaferrite film contains less than 2 wt % organic matter. The hexaferrite film does not require a binder. Discrete particles are not sintered or annealed together because the maximum processing temperature to fabricate the structure is 500° C. or less, such as 250° C. or less. The magnetic hexaferrite particles may contain barium hexaferrite (BaFe12O19) and/or strontium hexaferrite (SrFe12O19). The hexaferrite film may be characterized by a remanence-to-saturation magnetization ratio of at least 0.7. Methods of making and using the magnetically anisotropic structure are also described.

Abstract: An electronic assembly including: (a) wafer defining at least one cavity; (b) a chip disposed in the cavity; and (c) a metal heat spreader disposed in the cavity, the chip being embedded in the metal heat spreader; wherein the metal heat spreader has at least one elongate microstructure separated from a remainder of the metal heat spreader by at least one channel; wherein the metal heat spreader occupies an area within the cavity that is not occupied by the chip; and wherein the at least one elongate microstructure is configured and arranged in the cavity so as to improve thermal management of the chip by reducing stress across the chip as compared with a configuration and arrangement in which a heat spreader made of the metal and occupying the area within the cavity is a solid without channels. Also, a method for forming the electronic assembly.

Abstract: In some variations, the invention provides a method of depositing nanoparticles on a substrate, comprising: providing a substrate having a positive or negative surface charge; optionally depositing a polymer on the substrate, wherein the polymer has opposite charge polarity compared to the substrate; and simultaneously depositing first nanoparticles and second nanoparticles onto the substrate, wherein the first nanoparticles and the second nanoparticles have opposite charge polarities during depositing. Other variations provide a method of depositing a layer of nanoparticles on a substrate, the method comprising: providing a substrate having a positive or negative surface charge; providing faceted nanoparticles; preparing a nanoparticle solution containing the nanoparticles; and adjusting surface charge of the nanoparticles by changing the solution pH to reduce the magnitude of average zeta potential of the nanoparticles, thereby causing aggregation of the nanoparticles onto the substrate surface.

Abstract: A process for assembling microelectronic or semiconductor chips, comprising: providing a semiconductor chip having an active face with a connection pad; coating the active face of the semiconductor chip with a conformal dielectric material layer, such that the connection pad is completely coated by the conformal dielectric material layer; temporarily adhering the active face of the semiconductor chip to a carrier wafer; temporarily adhering the carrier wafer to a wafer-with-a-through-cavity such that the semiconductor chip extends into the through-cavity; assembling the semiconductor chip to the wafer-with-the-through-cavity by filling the through-cavity with a heat spreader material; releasing the assembled semiconductor chip and wafer-with-the-through-cavity from the carrier wafer; removing the conformal dielectric material layer from at least a portion of the connection pad; and forming an electrical connection to said at least a portion of the connection pad.

Abstract: An electronic assembly comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising an integrated circuit contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by direct contact of at least a side surface of said component chip with an attachment metal that fills at least a portion of said through-wafer cavity; said component chip comprising at least one component contact pad on said component chip bottom surface; and a conductor connecting said integrated circuit contact pad and said component contact pad.

Abstract: An integrated radar circuit comprising: a first substrate, of a first semiconductor material, said first substrate comprising an integrated transmit and receive radar circuit; a second substrate, of a second semiconductor material, said second substrate comprising at least on through-substrate cavity having cavity walls; at least one discrete transistor chip, of a third semiconductor material, said at least one discrete transistor chip having chip walls and being held in said at least one through-substrate cavity by a metal filling extending from at least one cavity wall to at least one chip wall; a conductor on said second substrate, electrically connecting a portion of said integrated transmit and receive radar circuit to a discrete transistor on said at least one discrete transistor chip.

Abstract: A radar system with frequency conversion includes a signal generator configured to generate an input signal at a first frequency. A transmitting interposer is configured to receive the input signal from the signal generator. The transmitting interposer includes a transmitting front-end module configured to upconvert the input signal at the first frequency to an outgoing radar signal at a second frequency greater than the first frequency, and a transmitting antenna module having a plurality of transmitting patches configured to radiate the outgoing radar signal. A receiving interposer is configured to transmit an output signal to the signal generator. The receiving interposer includes a receiving antenna module having a plurality of receiving patches configured to capture an incoming radar signal at the second frequency, and a receiving front-end module configured to downconvert the incoming radar signal at the second frequency to the output signal at the first frequency.

Abstract: An electronic assembly, comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising a wafer contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity joining the top and bottom wafer surfaces; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by direct contact of at least a side surface of said first component chip with an attachment metal that fills at least a portion of said through-wafer cavity; said component chip comprising at least one component contact pad on said component chip top surface; a first conductor connecting said wafer contact pad and said component contact pad.

Abstract: A method of forming concurrently openings in a substrate or wafer or a portion of substrate or wafer openings therein at least one of the openings has a relatively high aspect ratio and another one of the openings has a relatively low aspect ratio, the method comprising: bonding the substrate or wafer or a portion of substrate or wafer to a carrier substrate; forming a ring trench in the substrate or wafer or in a portion of the substrate or wafer, the ring trench having an outer perimeter that corresponds an outer perimeter of the another one of the openings having said relatively low aspect ratio and having an inner perimeter spaced from the outer perimeter by a predetermined distance; forming an opening in said substrate or wafer or in a portion of substrate or wafer having said high aspect ratio concurrently with the forming of the ring trench; and separating the substrate or wafer or in a portion of the substrate or wafer from the carrier substrate.

Abstract: A microwave electronic component comprising a substrate having top and bottom substrate surfaces; the substrate comprising an aperture between the top and bottom substrate surfaces; a metallic heat sink filling the aperture; a microwave integrated circuit having a top circuit surface with at least one microwave signal port and a bottom circuit surface in contact with the metallic heat sink; a signal line comprising at least a metallic via between the top and bottom substrate surfaces, and a top signal conductor arranged between the microwave signal port and the metallic via; wherein the dimensions and location of the metallic via are chosen such that the metallic via forms, together with the metallic heat sink, a first impedance-matched non-coaxial transmission line.

Abstract: A micro-optical bench includes a substrate having a multi-layer trench and a micro-lens aligned by and mounted to the substrate in the multi-layer trench.