Abstract: An RF circulator in combination with a RF integrated circuit, the RF integrated circuit having a plurality of RF waveguide or waveguide-like structures in or on the RF integrated circuit, the RF circulator comprising a disk of ferrite material disposed on a metallic material disposed on or in the RF integrated circuit, the disk of ferrite material extending away from the RF integrated circuit when disposed thereon, the metallic portion having a plurality of apertures therein adjacent the disk of ferrite material which, in use, are in electromagnetic communication with the disk of ferrite material and with the plurality of RF waveguide or waveguide-like structures, the disk of ferrite material being disposed in a metallic cavity.

Abstract: Some variations provide a method of making water-dispersed hexaferrite nanoparticles, comprising: providing a first salt containing iron, a second salt containing barium and/or strontium, and a third salt containing an anion or cation that is capable of forming a ligand with the hexaferrite nanoparticles; combining the first salt, second salt, third salt, and water to form a reaction mixture; subjecting the reaction mixture to effective reaction conditions to produce hexaferrite nanoparticles with the anion or cation in the third salt forming a ligand on the surface, so that the hexaferrite nanoparticles are dissolved and/or suspended in the reaction mixture; and obtaining water-dispersed hexaferrite nanoparticles with an average zeta potential of at least ±20 mV. The water-dispersed hexaferrite nanoparticles have a hexaferrite content of at least 85 wt %.

Abstract: A process for assembling microelectronic or semiconductor chips, comprising: providing a semiconductor chip having an active face with a connection pad; coating the active face of the semiconductor chip with a conformal dielectric material layer, such that the connection pad is completely coated by the conformal dielectric material layer; temporarily adhering the active face of the semiconductor chip to a carrier wafer; temporarily adhering the carrier wafer to a wafer-with-a-through-cavity such that the semiconductor chip extends into the through-cavity; assembling the semiconductor chip to the wafer-with-the-through-cavity by filling the through-cavity with a heat spreader material; releasing the assembled semiconductor chip and wafer-with-the-through-cavity from the carrier wafer; removing the conformal dielectric material layer from at least a portion of the connection pad; and forming an electrical connection to said at least a portion of the connection pad.

Abstract: A radar system with frequency conversion includes a signal generator configured to generate an input signal at a first frequency. A transmitting interposer is configured to receive the input signal from the signal generator. The transmitting interposer includes a transmitting front-end module configured to upconvert the input signal at the first frequency to an outgoing radar signal at a second frequency greater than the first frequency, and a transmitting antenna module having a plurality of transmitting patches configured to radiate the outgoing radar signal. A receiving interposer is configured to transmit an output signal to the signal generator. The receiving interposer includes a receiving antenna module having a plurality of receiving patches configured to capture an incoming radar signal at the second frequency, and a receiving front-end module configured to downconvert the incoming radar signal at the second frequency to the output signal at the first frequency.

Abstract: A method of forming concurrently openings in a substrate or wafer or a portion of substrate or wafer openings therein at least one of the openings has a relatively high aspect ratio and another one of the openings has a relatively low aspect ratio, the method comprising: bonding the substrate or wafer or a portion of substrate or wafer to a carrier substrate; forming a ring trench in the substrate or wafer or in a portion of the substrate or wafer, the ring trench having an outer perimeter that corresponds an outer perimeter of the another one of the openings having said relatively low aspect ratio and having an inner perimeter spaced from the outer perimeter by a predetermined distance; forming an opening in said substrate or wafer or in a portion of substrate or wafer having said high aspect ratio concurrently with the forming of the ring trench; and separating the substrate or wafer or in a portion of the substrate or wafer from the carrier substrate.

Abstract: An interposer includes an interposer substrate having a series of vias, and a series of metallic interconnects in the series of vias. The interposer substrate has a first surface and a second surface opposite the first surface. The interposer substrate includes a dielectric material. A first pitch of the series of vias at a first end of the series of vias is different than a second pitch of the series of vias at a second end of the series of vias.

Abstract: An RF circulator in combination with a RF integrated circuit, the RF integrated circuit having a plurality of RF waveguide or waveguide-like structures in or on the RF integrated circuit, the RF circulator comprising a disk of ferrite material disposed on a metallic material disposed on or in the RF integrated circuit, the disk of ferrite material extending away from the RF integrated circuit when disposed thereon, the metallic portion having a plurality of apertures therein adjacent the disk of ferrite material which, in use, are in electromagnetic communication with the disk of ferrite material and with the plurality of RF waveguide or waveguide-like structures, the disk of ferrite material being disposed in a metallic cavity.

Abstract: A recursive metal-embedded chip assembly (R-MECA) process and method is described for heterogeneous integration of multiple die from diverse device technologies. The recursive aspect of this integration technology enables integration of increasingly-complex subsystems while bridging different scales for devices, interconnects and components. Additionally, the proposed concepts include high thermal management performance that is maintained through the multiple recursive levels of R-MECA, which is a key requirement for high-performance heterogeneous integration of digital, analog mixed signal and RF subsystems. At the wafer-scale, chips from diverse technologies and different thicknesses are initially embedded in a metal heat spreader surrounded by a mesh wafer host. An embodiment uses metal embedding on the backside of the chips as a key differentiator for high-density integration, and built-in thermal management.

Abstract: A microfabricated laminated conductor, comprising at least two flat metallic conductors held together parallel by their edges by a first dielectric material anchor, such that there exists a gap of between several nanometers and several micrometers between most of the at least two flat metallic conductors.

Abstract: An integrated component having a metallic interlocking structure; the integrated component comprising an integrated circuit integrated in a substrate having a top surface; the integrated circuit comprising a first conducting line; and a first metallic interlocking structure comprising a first array of free-standing metallic columns formed on said top surface and electrically connected to said first conducting line.

Abstract: An electronic assembly, comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising a wafer contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity joining the top and bottom wafer surfaces; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by an attachment material attaching at least one wall of the through-wafer cavity to at least one of the component chip bottom surface and a component chip side surface; said component chip comprising at least one component contact pad on said component chip top substrate; a first conductor connecting said wafer contact pad and said component contact pad.

Abstract: A microfabricated laminated conductor, comprising at least two flat metallic conductors held together parallel by their edges by a first dielectric material anchor, such that there exists a gap of between several nanometers and several micrometers between most of the at least two flat metallic conductors.

Abstract: A method for fabricating high-resolution features in a deep recess includes etching a cavity in a substrate, fabricating at least one focusing pattern on a bottom of the cavity, wherein fabricating the focusing pattern comprises coating a first photoresist on the bottom of the cavity, patterning the first photoresist to define a focusing etch area using contact lithography, and etching the focusing etch area, coating a second photoresist on the bottom of the cavity, using the focusing pattern to focus a high resolution lithography tool at the bottom of the cavity to pattern the second photoresist to define a microfabrication feature area; and forming a microfabrication feature in the microfabrication feature area.

Abstract: A recursive metal-embedded chip assembly (R-MECA) process and method is described for heterogeneous integration of multiple die from diverse device technologies. The recursive aspect of this integration technology enables integration of increasingly-complex subsystems while bridging different scales for devices, interconnects and components. Additionally, the proposed concepts include high thermal management performance that is maintained through the multiple recursive levels of R-MECA, which is a key requirement for high-performance heterogeneous integration of digital, analog mixed signal and RF subsystems. At the wafer-scale, chips from diverse technologies and different thicknesses are initially embedded in a metal heat spreader surrounded by a mesh wafer host. An embodiment uses metal embedding on the backside of the chips as a key differentiator for high-density integration, and built-in thermal management.

Abstract: There is provided an integrated RF subsystem including a chip substrate, a circuit patterned on a first surface of the chip substrate, a probe electrically integrated with the circuit on a first side of the chip substrate, a frame at a second side of the chip substrate defining a first cavity underneath the circuit.

Abstract: An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.

Abstract: A method for fabricating high-resolution features in a deep recess includes etching a cavity in a substrate, fabricating at least one focusing pattern on a bottom of the cavity, wherein fabricating the focusing pattern comprises coating a first photoresist on the bottom of the cavity, patterning the first photoresist to define a focusing etch area using contact lithography, and etching the focusing etch area, coating a second photoresist on the bottom of the cavity, using the focusing pattern to focus a high resolution lithography tool at the bottom of the cavity to pattern the second photoresist to define a microfabrication feature area; and forming a microfabrication feature in the microfabrication feature area.

Abstract: A method for wafer level packaging includes forming one or more die, forming a plated metal ring (PMR) on each die, forming a cover wafer (CW), the CW having one or more plated seal rings, forming a body wafer (BW), the BW having cavities and a metal layer on a first side of the BW, aligning a respective die to the CW so that a PMR on the respective die is aligned to a respective plated seal ring (PSR) on the CW, bonding the PMR on the respective die to the respective PSR, aligning the BW to the CW so that a respective cavity of the BW surrounds each respective die bonded to the CW and so that the metal layer on the BW is aligned with at least one PSR on the CW, and bonding the metal layer on the first side of the BW to the PSR on the CW. Each PMR has a first height and each PSR has a second height.

Abstract: An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.

Abstract: A method for forming a wafer level heat spreader includes providing a mesh wafer, the mesh wafer having a plurality of openings and mesh regions between the openings, bonding the mesh wafer to a backside of an integrated circuit (IC) wafer, the IC wafer comprising a plurality of circuits; and electroplating a heat sink material through the plurality of openings and onto to the backside of the IC wafer.