Abstract: A III-nitride power semiconductor based heterojunction device comprising a substrate, a first terminal, a second terminal, a control terminal configured to receive an input switching signal during an active mode of operation and to not receive the input switching signal during a stand-by mode of operation, and an active heterojunction transistor formed on the substrate.

Abstract: A fluid sensor for sensing a concentration or composition of a fluid, the sensor comprising a first temperature sensing element located on or within a first dielectric membrane and a second temperature sensing element located on or within a second dielectric membrane. An output circuit is configured to measure a differential signal between the first temperature sensing element and the second temperature sensing element. The fluid sensor comprises a first region configured to be exposed to the fluid, and a second region configured to be isolated from the fluid, where the first dielectric membrane is located in the first region, such that in use, the first dielectric membrane is exposed to the fluid, and wherein the second dielectric membrane is located in the second region such that in use, the second dielectric membrane is isolated from the fluid.

Abstract: We disclose herein a flow sensor comprising: a first substrate comprising an etched portion, a dielectric region located on a first side of the first substrate, wherein the dielectric region comprises at least one dielectric membrane located over the etched portion of the first substrate, a sensing element located on or within the dielectric membrane, and a second substrate adjoining a second side of the first substrate. The first side of the first substrate and the second side of the first substrate are opposite sides. The first substrate and the second substrate cooperate to form a sensing channel through the flow sensor.

Abstract: We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on th

Abstract: Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.

Abstract: An integrated circuit is provided which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.

Abstract: A fluid sensor for sensing a concentration or composition of a fluid, the sensor comprising: a semiconductor substrate comprising a first etched portion and a second etched portion; a dielectric region located on the semiconductor substrate, wherein the dielectric region comprises a first dielectric membrane located over the first etched portion of the semiconductor substrate, and a second dielectric membrane located over the second etched portion of the semiconductor substrate; two temperature sensing elements on or within the first dielectric membrane and two temperature sensing elements on or within the second dielectric membrane; an output circuit configured to measure a differential signal between the two temperature sensing elements of the first dielectric membrane and the two temperature sensing elements of the second dielectric membrane; wherein the first dielectric membrane is exposed to the fluid and the second dielectric membrane is isolated from the fluid.

Abstract: The present application relates to a smell sensing system (100) comprising a smell delivery device (104) for delivering an olfactory output (110). The smell delivery device (104) comprises a delivery channel (3) for receiving a substance (5a) from a canister (5), the substance (5a) configured to produce an olfactory output (114). The smell delivery device (104) also comprises an output component (7) through which the substance (5a) is emitted. The smell delivery device (104) also comprises one or more airflow generating elements (13) configured to generate airflow to transport the substance (5a) from the canister (5) to the output component (7). The smell sensing system (100) also comprises a smell sensing device (102) for detecting the olfactory output (110) delivered by the smell delivery device (104).

Abstract: The present disclosure relates to an edge detection circuit configured to receive an input signal comprising one or more falling or falling edges and provide an output signal comprising pulses or spikes corresponding to the one or more rising or falling edges. The edge detection circuit comprises a passive differentiator circuit configured to receive an input and provide a differentiator output signal that that is proportional to the rate of change of the input, and a comparator circuit operably connected to a voltage source. The comparator circuit is configured to receive the differentiator output signal, compare the differentiator output signal to a threshold voltage; and output a pulse or spike signal based on the comparison to the threshold voltage.

Abstract: We describe an integrated circuit is disclosed which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.

Abstract: We describe a smart high voltage/power III-nitride semiconductor based diode or rectifier comprising first and second terminals, and further comprising an active device (e.g. a transistor such as a GaN HEMT transistor), a sensing device (e.g. a sensing diode/transistor), a sensing load (e.g. a resistor), wherein the smart high voltage/power III-nitride semiconductor based diode or rectifier is configured to output a sensing signal corresponding a current through the sensing device and/or a voltage drop across the sensing load, wherein the sensing signal is indicative of a current flowing between the first and second terminal when a bias is applied between the first and second terminals.

Abstract: We describe a heterojunction based half bridge apparatus formed within a single active area comprising a first heterojunction device and a second heterojunction device, each heterojunction device comprising a drain and a source, each drain comprising a drain contact and each source comprising a source contact; wherein the drain contact of the first heterojunction device and the source contact of the second heterojunction device comprise a common contact. The half bridge apparatus according to the present disclosure may be advantageously more compact and more reliable than existing heterojunction based half bridges.

Abstract: A semiconductor device includes a type IV semiconductor base substrate, a first type III-V semiconductor layer formed on a first surface of the base substrate, and a second type III-V semiconductor layer with a different bandgap as the first type III-V being formed on the first type III-V semiconductor layer. The semiconductor device further includes first and second electrically conductive device terminals each being formed on the second type III-V semiconductor layer and each being in ohmic contact with the two-dimensional charge carrier gas. The base substrate includes a dielectric layer formed directly on a lower region of type IV semiconductor material, and a highly-doped layer of type IV semiconductor material formed directly on the dielectric layer.

Abstract: A gas sensing device comprising a substrate comprising an etched cavity portion and a substrate portion, a dielectric layer disposed on the substrate, wherein the dielectric layer comprises a dielectric membrane, wherein the dielectric membrane is adjacent to the etched cavity portion of the substrate, a heater located within the dielectric layer; a material for sensing a gas; and one or more polysilicon electrodes coupled with the material for sensing a gas.

Abstract: A III-nitride semiconductor based heterojunction power device including: a first heterojunction transistor formed on a substrate, and a second heterojunction transistor formed on the substrate. One of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor. The enhancement mode transistor acts as a main power switch, and the depletion mode transistor acts as a start-up component.

Abstract: There is disclosed herein a flow sensor comprising: a first substrate comprising an etched portion; a dielectric layer located on the first substrate, where the dielectric layer comprises at least one dielectric membrane located over the etched portion of the first substrate; a first heating element and a second heating element located on or within the dielectric membrane; and a controller coupled with the first heating element and the second heating element. The first heating element and the second heating element are arranged to intersect one another within or over an area of the dielectric membrane. The controller is configured to: take a measurement from the second heating element; determine a calibration parameter using the measurement from the second heating element; take a measurement from the first heating element; and determine a flow rate through the flow sensor using the determined calibration parameter and the measurement from the first heating element.

Abstract: A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

Abstract: A heterojunction device, includes a substrate (4); a Ill-nitride semiconductor region located longitudinally above or over the substrate and including a heterojunction having a two-dimensional carrier gas; first (8) and second (9) laterally spaced terminals operatively connected to the semiconductor; a gate structure (11) of first conductivity type located above or longitudinally over the semiconductor region and laterally spaced between the first and second terminals; a control gate terminal (10) operatively connected to the gate structure, a potential applied to the control gate terminal modulates and controls a current flow through the carrier gas between the terminals, the carrier gas being a second conductivity type; an injector of carriers (101) of the first conductivity type laterally spaced away from the second terminal; and a floating contact layer (102) located over the carrier gas and laterally spaced away from the second terminal and operatively connected to the injector and the semiconductor regi

Abstract: A semiconductor device includes a type IV semiconductor base substrate, a first type III-V semiconductor layer formed on a first surface of the base substrate, and a second type III-V semiconductor layer with a different bandgap as the first type III-V being formed on the first type III-V semiconductor layer. The semiconductor device further includes first and second electrically conductive device terminals each being formed on the second type III-V semiconductor layer and each being in ohmic contact with the two-dimensional charge carrier gas. The base substrate includes a first highly doped island that is disposed directly beneath the second device terminal and extends to the first surface of the base substrate. The first highly-doped island is laterally disposed between portions of semiconductor material having a lower net doping concentration than the first highly-doped island.

Abstract: We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on th