Abstract: We disclose herein a gas sensor comprising a catalyst material; a temperature detector configured to measure a change in temperature of the catalyst material; and a plurality of electrodes configured to measure the current and/or resistance of the catalytic material. The gas sensor can be formed using CMOS or CMOS-SOI technologies.

Abstract: We disclose herewith a heterostructure-based infra-red (IR) device comprising a substrate comprising an etched portion and a substrate portion; a device region on the etched portion and the substrate portion, the device region comprising a membrane region which is an area over the etched portion of the substrate. At least one heterostructure-based element is formed at least partially within or on the membrane region and the heterostructure-based element comprises at least one two dimensional carrier gas.

Abstract: We disclose herein a CMOS-based sensing device comprising a substrate comprising an etched portion, a first region located on the substrate, wherein the first region comprises a membrane region formed over an area of the etched portion of the substrate, a flow sensor formed within the membrane region and a pressure sensor formed within the membrane region.

Abstract: We disclose an array of Infra-Red (IR) detectors comprising at least one dielectric membrane formed on a semiconductor substrate comprising an etched portion; at least two IR detectors, and at least one patterned layer formed within or on one or both sides of the said dielectric membrane for controlling the IR absorption of at least one of the IR detectors. The patterned layer comprises laterally spaced structures.

Abstract: It is disclosed herein a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device is made using partly CMOS or CMOS based processing steps, and it includes a semiconductor substrate, a dielectric region over the semiconductor substrate, a heater within the dielectric region and a patterned layer of noble metal above the dielectric region. The method includes the deposition of a photoresist material over the dielectric region, and patterning the photo-resist material to form a patterned region over the dielectric region. The steps of depositing the photo-resist material and patterning the photo-resist material may be performed in sequence using similar photolithography and etching steps to those used in a CMOS process. The resulting semiconductor device is then subjected to further processing steps which ensure that a dielectric membrane and a metal structure within the membrane are formed in the patterned region over the dielectric region.

Abstract: We disclose a micro-hotplate comprising a substrate comprising an etched portion and a substrate portion and a dielectric region over the substrate. The dielectric region comprises first and second portions. The first portion is adjacent to the etched portion of the substrate and the second portion is adjacent to the substrate portion of the substrate. The micro-hotplate further comprises a heater formed in the dielectric region, and a ring structure formed within and/or over the dielectric region such that the ring structure is coupled with the first and second portions of the dielectric region.

Abstract: A power semiconductor device and method for making same are disclosed. The device includes a source bonding pad and a drain bonding pad, a drain metallization structure including a drain field plate connected to the drain bonding pad, and a source metallization structure comprising a source field plate connected to the source bonding pad. At least a portion of at least one of the bonding pads is situated directly over an active area. A dimension of at least one of the field plates varies depending upon the structure adjacent to the field plate.

Abstract: We disclose herein a CMOS-based flow sensor comprising a substrate comprising an etched portion; a dielectric region located on the substrate, wherein the dielectric region comprises a dielectric membrane over an area of the etched portion of the substrate; a p-n junction type device formed within the dielectric membrane, wherein the p-n junction type device is configured to operate as a temperature sensing device.

Abstract: We disclose herein an infra-red (IR) detector comprising a substrate comprising at least one etched portion and a substrate portion; a dielectric layer disposed on the substrate. The dielectric layer comprises at least one dielectric membrane, which is adjacent to the etched portion of the substrate. The detector further comprises a first sensing area and a second sensing area each located in a dielectric membrane and a plurality of thermocouples. At least one thermocouple comprises first and second thermal junctions. The first thermal junction is located in or on the first sensing area and the second thermal junction is located in or on the second sensing area.

Abstract: We disclose herewith a heterostructure-based sensor comprising a substrate comprising an etched portion and a substrate portion; a device region located on the etched portion and the substrate portion; the device region comprising at least one membrane region which is an area over the etched portion of the substrate. At least one heterostructure-based element is located at least partially within or on the at least one membrane region, the heterostructure-based element comprising at least one two dimensional (2D) carrier gas.

Abstract: We disclose herewith a heterostructure-based infra-red (IR) device comprising a substrate comprising an etched portion and a substrate portion; a device region on the etched portion and the substrate portion, the device region comprising a membrane region which is an area over the etched portion of the substrate. At least one heterostructure-based element is formed at least partially within or on the membrane region and the heterostructure-based element comprises at least one two dimensional carrier gas.

Abstract: A heterojunction power device includes a substrate; a III-nitride semiconductor region over the substrate; a source operatively connected to the semiconductor region; a drain operatively connected to the semiconductor region; a gate between the source and drain and over the semiconductor region. The source is in contact with a first portion located between the source and gate and having a two dimensional carrier gas. The drain is in contact with a second portion located between the drain and gate and having a two dimensional carrier gas. At least one of the first and second portions has a trench having vertical sidewalls and formed within the semiconductor region; mesa regions extend away from each sidewall of the trench. The two dimensional carrier gas is located alongside the mesa regions and the trench. At least one of the source and drain is in contact with the respective two dimensional carrier gas.

Abstract: A thermal conductivity sensing device (1) is disclosed, along with a method for operation of the thermal conductivity sensing device and use of the thermal conductivity sensing device in a system for gas chromatography and a method of carrying out gas chromatography. The thermal conductivity sensing device is for use in sensing one or more gaseous components in a flowing gaseous environment. The device has a first sensor (4B) and a second sensor (4A) for exposure to the same flowing gaseous environment (G). The first sensor has an associated flow altering means (20) to affect gas flow at least at part of the surface of the first sensor, to be different to gas flow at the surface of the second sensor. Each sensor provides an output relating to heat transfer between a surface of the sensor and the gaseous environment. The device is operable to compare outputs of the first and second sensors. The sensor is able to reduce the effects of bulk convection of the flowing gas on thermal conductivity measurements.

Abstract: We disclose herein an infra-red (IR) detector comprising a substrate comprising at least one etched portion and a substrate portion; a dielectric layer disposed on the substrate. The dielectric layer comprises at least one dielectric membrane, which is adjacent to the etched portion of the substrate. The detector further comprises a first sensing area and a second sensing area each located in a dielectric membrane and a plurality of thermocouples. At least one thermocouple comprises first and second thermal junctions. The first thermal junction is located in or on the first sensing area and the second thermal junction is located in or on the second sensing area.

Abstract: The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.

Abstract: A power semiconductor device and method for making same are disclosed. The device includes a source bonding pad and a drain bonding pad, a drain metallization structure including a drain field plate connected to the drain bonding pad, and a source metallization structure comprising a source field plate connected to the source bonding pad. At least a portion of at least one of the bonding pads is situated directly over an active area. A dimension of at least one of the field plates varies depending upon the structure adjacent to the field plate.

Abstract: We disclose herein an infra-red (IR) device comprising a substrate comprising an etched cavity portion and a substrate portion; a dielectric layer disposed on the substrate. The dielectric layer comprises a dielectric membrane which is adjacent, or directly above, or below the etched cavity portion of the substrate. The device further comprises a reflective layer on or in or above or below the dielectric membrane to enhance emission or absorption of infrared light at one or more wavelengths.

Abstract: We disclose an Infrared (IR) device comprising a first substrate comprising a first cavity; a dielectric layer disposed on the first substrate; a second substrate disposed on the dielectric layer and on the opposite side of the first substrate, the second substrate having a second cavity. The device further comprises an optically transmissive layer attached to one of the first and second substrates; a further layer provided to another of the first and second substrates so that the IR device is substantially closed. Holes are provided through the dielectric layer so that a pressure in the first cavity is substantially the same level as a pressure in the second cavity.

Abstract: We disclose herein an environmental sensor system comprising an environmental sensor comprising a first heater and a second heater in which the first heater is configured to consume a lower power compared to the second heater. The system also comprises a controller coupled with the environmental sensor. The controller is configured to detect if a measured value of a targeted environmental parameter is present. The controller is configured to switch on at least one of the first and second heaters based on the presence and/or result of the measured value of the targeted environmental parameter.

Abstract: There are disclosed herein various implementations of a bipolar semiconductor device with multi-trench enhancement regions. Such a bipolar semiconductor device includes a drift region having a first conductivity type situated over an anode layer having an opposite, second conductivity type. The device also includes a first control trench extending through an inversion region having the second conductivity type, and further extending into the drift region, the first control trench being adjacent to cathode diffusions. In addition, the device includes first and second depletion trenches, each having a depletion electrode, the first depletion trench being situated between the second depletion trench and the first control trench. An enhancement region having the first conductivity type is localized in the drift region and extends from the first control trench to the first second depletion trench and further from the first depletion trench to the second depletion trench.