Abstract: A method is disclosed. The method includes: obtaining a circuit design including a plurality of 2D cells of a 2D cell library; partitioning the plurality of 2D cells of the circuit design into a first group assigned to a first tier and a second group assigned to a second tier; swapping the 2D cells assigned to the first tier with corresponding 3D cells of a first type 3D cell library respectively; and swapping the 2D cells assigned to the second tier with corresponding 3D cells of a second type 3D cell library respectively; wherein at least one of the obtaining, partitioning, and swapping is performed using a processor. An associated system is also disclosed.

Abstract: A method performed by at least one processor includes selecting a pin in a cell, determining a type of the pin, assigning a first pin access and a second pin access of the pin to a same patterning group at different patterning tracks when the pin is determined to be a cross-track pin, determining whether a pin access of a first pin and a pin access of a second pin disposed adjacent to the first pin in the cell are on a same patterning track, separating the first pin and the second pin from each other by a first predetermined distance when the pin accesses are determined to not be on a same patterning track, and separating the first pin and the second pin from each other by a second predetermined distance when the pin accesses are determined to be on a same patterning track.

Abstract: A method of forming an integrated circuit is disclosed. The method includes generating, by a processor, a layout design of the integrated circuit, outputting the integrated circuit based on the layout design, and removing a portion of a conductive structure of the integrated circuit to form a first conductive structure and a second conductive structure. Generating the layout design includes generating a standard cell layout having a set of conductive feature layout patterns, placing a power layout pattern with the standard cell layout according to at least one design criterion, and extending at least one conductive feature layout pattern of the set of conductive feature layout patterns in at least one direction to a boundary of the power layout pattern. The power layout pattern includes a cut feature layout pattern. The cut feature layout pattern identifies a location of the removed portion of the conductive structure of the integrated circuit.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a wire cut between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the wire cut separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: A method of generating a layout of an IC includes identifying a target pin in a first cell in an IC layout, the first cell being adjacent to a second cell and sharing a boundary with the second cell, and determining whether or not the target pin is capable of being extended into the second cell. Based on a determination that the target pin is capable of being extended into the second cell, the target pin is modified to include an extension into the second cell, the target pin thereby crossing the shared boundary. At least one of the identifying, determining, or modifying is executed by a processor of a computer.

Abstract: A method includes using a processor to placing a cell having a first conductive feature and a second conductive feature on an integrated circuit layout. A length of the first conductive feature is extended, by using the processor, to form a staggered configuration. A set of instructions for manufacturing an integrated circuit based upon the integrated circuit layout is generated, and the set of instructions is stored in a non-transitory machine readable storage medium.

Abstract: An integrated circuit includes a first region and a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a first via coupled to the first conductive structure. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first or second region. The power structure includes a second conductive structure extending in the first direction and overlapping a boundary between the first region and the second region. The first conductive structure and the second conductive structure are aligned in a second direction. The first conductive structure and the second conductive structure are separated from each other in the first direction by a distance greater than a minimum spacing requirement of the first conductive structure and the second conductive structure.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: Exemplary embodiments for multiple standard cell libraries are disclosed that include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations have similar functionality as their one or more standard cells but are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for analog circuitry and/or digital circuitry of an electronic device. In an exemplary embodiment, a semiconductor foundry and/or semiconductor technology node can impose one or more electronic design constraints on the placement of the one or more standard cells onto an electronic device design real estate.

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: A computer implemented method for routing a first path in a circuit design is presented. The method includes iteratively building a multitude of partial-paths to route the first path by adding an incremental length to a selected previously built partial-path when the computer is invoked to route the first path in the circuit design, the adding being performed in accordance with at least a first design rule. The multitude of partial-paths start at a first location. The method further includes comparing each of the multitude of partial-paths to each other when the multitude of partial-paths end on a common second location different from the first location, and saving one of the multitude of partial-paths that leads to a shortest first path. The method further includes eliminating one of the multitude of partial-paths that are not selected to lead to the shortest first path.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A method (of expanding a set of standard cells which comprise a library, the library being stored on a non-transitory computer-readable medium) includes: selecting one amongst ad hoc groups of elementary standard cells which are recurrent resulting in a selected group such that the elementary standard cells in the selected group having connections so as to represent a corresponding logic circuit, each elementary standard cell representing a logic gate, and the selected group corresponding providing a selected logical function which is representable correspondingly as a selected Boolean expression; generating, in correspondence to the selected group, one or more macro standard cells; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells; and wherein at least one aspect of the method is executed by a processor of a computer.

Abstract: Computer-implemented systems and methods for generating a multiple patterning lithography (MPL) compliant integrated circuit layout are provided. A plurality of integrated circuit (IC) cells are assembled to form an IC layout. The IC layout includes at least two IC cells that abut one another. After the assembling of the IC cells, a decomposition algorithm is executed to assign multiple colors to design shapes within the IC layout. Multiple patterning coloring conflicts are detected in the IC layout after the assigning of the colors to the design shapes. A fixing algorithm is executed, under which a conflict present in two abutting IC cells is fixed by flipping or shifting at least one of the abutting IC cells.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A semiconductor device comprising active areas and a structure. The active areas are formed as predetermined shapes on a substrate and arranged relative to a grid having first and second tracks which are substantially parallel to corresponding orthogonal first and second directions; The active areas are organized into instances of a first row having a first conductivity and a second row having a second conductivity. Each instance of the first row and of the second row includes a corresponding first and second number predetermined number of the first tracks. The structure has at least two contiguous rows including: at least one instance of the first row; and at least one instance of the second row. In the first direction, the instance(s) of the first row have a first width and the instance(s) of the second row a second width substantially different than the first width.

Abstract: A method of modifying a cell includes identifying a maximum overlapped pin group. The method further includes determining a number of pins in the maximum overlapped pin group. The method further includes determining a span region of the maximum overlapped pin group. The method further includes comparing the number of pins and the span region to determine a global tolerance of the cell. The method further includes increasing a length of at least one pin of the maximum overlapped pin group in response to the global tolerance failing to satisfy a predetermined threshold. The method further includes fabricating a mask based on the increased length of the at least one pin.

Abstract: A method performed by at least one processor includes selecting a pin in a cell, determining a type of the pin, assigning a first pin access and a second pin access of the pin to a same patterning group at different patterning tracks when the pin is determined to be a cross-track pin, determining whether a pin access of a first pin and a pin access of a second pin disposed adjacent to the first pin in the cell are on a same patterning track, separating the first pin and the second pin from each other by a first predetermined distance when the pin accesses are determined to not be on a same patterning track, and separating the first pin and the second pin from each other by a second predetermined distance when the pin accesses are determined to be on a same patterning track.

Abstract: Computer-implemented systems and methods for generating a multiple patterning lithography (MPL) compliant integrated circuit layout are provided. A plurality of integrated circuit (IC) cells are assembled to form an IC layout. The IC layout includes at least two IC cells that abut one another. After the assembling of the IC cells, a decomposition algorithm is executed to assign multiple colors to design shapes within the IC layout. Multiple patterning coloring conflicts are detected in the IC layout after the assigning of the colors to the design shapes. A fixing algorithm is executed, under which a conflict present in two abutting IC cells is fixed by flipping or shifting at least one of the abutting IC cells.

Abstract: A method of global connection routing includes determining a global connection tolerance of a cell for use in a circuit layout, wherein the cell comprises a plurality of pins, and a plurality of routing tracks are defined with respect to the cell. The method further includes determining a number of blocked tracks within the cell. The method further includes comparing the global connection tolerance with the number of blocked tracks. The method further includes adjusting a location of the cell within the circuit layout if the global connection tolerance and the number of blocked tracks fail to satisfy a predetermined condition.