Patents by Inventor Fong-Yuan Chang

Fong-Yuan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8561002
    Abstract: Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a net comprising a set of pins, a first wire for routing the net is generated, the set of pins comprising the net is partitioned into one or more groups based at least in part on a cost function, a second wire that connects to the first wire is generated for each group of the net, and a third wire that connects each pin to the second wire of its group is generated for each pin of each group of the net.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: October 15, 2013
    Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.
    Inventors: Fong-Yuan Chang, Wei-Shun Chuang, Sheng-Hsiung Chen, Hsian-Ho Chang, Ruey-Shi Rau
  • Patent number: 8407647
    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: March 26, 2013
    Assignees: Springsoft, Inc., Springsoft USA, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Patent number: 8336001
    Abstract: A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: December 18, 2012
    Assignee: Springsoft, Inc.
    Inventors: Fong-Yuan Chang, Wai-Kei Mak, Ren-Song Tsay
  • Publication number: 20120137265
    Abstract: Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a plurality of nets and a specification of a set of routing tracks available for main spines, a main spine routing track is assigned to each of the plurality of nets based at least in part on a cost function and main spine wires are generated on the assigned main spine routing tracks for each of the plurality of nets.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 31, 2012
    Applicant: SPRINGSOFT, INC.
    Inventors: Fong-Yuan Chang, Wei-Shun Chuang, Sheng-Hsiung Chen, Hsian-Ho Chang, Ruey-Shi Rau
  • Publication number: 20120137264
    Abstract: Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a net comprising a set of pins, a first wire for routing the net is generated, the set of pins comprising the net is partitioned into one or more groups based at least in part on a cost function, a second wire that connects to the first wire is generated for each group of the net, and a third wire that connects each pin to the second wire of its group is generated for each pin of each group of the net.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 31, 2012
    Applicant: SPRINGSOFT, INC.
    Inventors: Fong-Yuan Chang, Wei-Shun Chuang, Sheng-Hsiung Chen, Hsian-Ho Chang, Ruey-Shi Rau
  • Patent number: 8015522
    Abstract: An engineering change order (ECO) modifying an IC having spare cell instances is implemented by converting active cell instances implementing portions of the IC to be deleted into additional spare cell instances, by creating a technology independent behavioral model of portions of the IC to be added, by selecting spare cell instances to implement the behavior model, and by routing nets to the selected spare cell instances in a way that minimizes a number of metal layers of the IC that are modified.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: September 6, 2011
    Assignee: Springsoft USA, Inc.
    Inventors: Hsin-Po Wang, Yu-Sheng Lu, Fong-Yuan Chang, Yi-Der Lin, Sung-Han Tsai, Ru Lin Yang, Chun-Cheng Chi, Hsueh Liang Hsu
  • Publication number: 20110154282
    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.
    Type: Application
    Filed: December 16, 2010
    Publication date: June 23, 2011
    Inventors: Fong-Yuan CHANG, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Publication number: 20110107278
    Abstract: A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest
    Type: Application
    Filed: October 27, 2010
    Publication date: May 5, 2011
    Inventors: Fong-Yuan Chang, Wai-Kei Mak, Ren-Song Tsay
  • Publication number: 20090178013
    Abstract: An engineering change order (ECO) modifying an IC having spare cell instances is implemented by converting active cell instances implementing portions of the IC to be deleted into additional spare cell instances, by creating a technology independent behavioral model of portions of the IC to be added, by selecting spare cell instances to implement the behavior model, and by routing nets to the selected spare cell instances in a way that minimizes a number of metal layers of the IC that are modified.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 9, 2009
    Applicant: SPRINGSOFT USA, INC.
    Inventors: Hsin-Po Wang, Yu-Sheng Lu, Fong-Yuan Chang, Yi-Der Lin, Sung-Han Tsai, Ru Lin Yang, Chun-Cheng Chi, Hsueh Liang Hsu
  • Publication number: 20030088484
    Abstract: The present invention provides a website service method. First, a specific demand event to be searched is set at one's own server, and several website addresses, BBS addresses, or related server addresses are inputted. A searching program then actively collects related data, and stores the data into a database. Next, the server picks out communication information and mating data and then actively invites the supplier and the demander to enter the website. After the supplier and the demander are informed, they can connect to the website to register and input article data or demand conditions. The website performs relational mating of supply and demand and then displays the mating result. If the requirements of the supplier and the demander are met, they can contact each other through data provided by the database. Supply and demand can thus be more effectively and quickly accomplished.
    Type: Application
    Filed: November 6, 2001
    Publication date: May 8, 2003
    Inventors: Fong-Yuan Chang, Ing-Kai Huang