Abstract: Disclosed herein are methods and devices for defeating buffer overflow problems in multicore processors. In one embodiment, a processor implemented within a multicore processor integrated circuit (IC) is disclosed. The processor includes an instruction register and selection circuitry including a hardware latch operable to thwart a buffer overflow attack. The selection circuitry is electrically coupled with the instruction register. The selection circuitry is configured for: providing decrypted instructions to the instruction register when the hardware latch is in a first state and providing un-decrypted instructions to the instruction register when the hardware latch is in a second state. The coupling of the selection circuitry can be directly to the instruction register of a processor core, or indirectly by directing the output of the selection circuitry to cache memory inside the processor IC so that the instruction register only receives decrypted instructions from the cache memory.

Abstract: A method for changing a processor instruction randomly, covertly, and uniquely, so that the reverse process can restore it faithfully to its original form, making it virtually impossible for a malicious user to know how the bits are changed, preventing them from using a buffer overflow attack to write code with the same processor instruction changes into said processor's memory with the goal of taking control of the processor. When the changes are reversed prior to the instruction being executed, reverting the instruction back to its original value, malicious code placed in memory will be randomly altered so that when it is executed by the processor it produces chaotic, random behavior that will not allow control of the processor to be compromised, eventually producing a processing error that will cause the processor to either shut down the software process where the code exists to reload, or reset.

Abstract: A method for changing a processor instruction randomly, covertly, and uniquely, so that the reverse process can restore it faithfully to its original form, making it virtually impossible for a malicious user to know how the bits are changed, preventing them from using a buffer overflow attack to write code with the same processor instruction changes into said processor's memory with the goal of taking control of the processor. When the changes are reversed prior to the instruction being executed, reverting the instruction back to its original value, malicious code placed in memory will be randomly altered so that when it is executed by the processor it produces chaotic, random behavior that will not allow control of the processor to be compromised, eventually producing a processing error that will cause the processor to either shut down the software process where the code exists to reload, or reset.

Abstract: A method for changing a processor instruction randomly, covertly, and uniquely, so that the reverse process can restore it faithfully to its original form, making it virtually impossible for a malicious user to know how the bits are changed, preventing them from using a buffer overflow attack to write code with the same processor instruction changes into said processor's memory with the goal of taking control of the processor. When the changes are reversed prior to the instruction being executed, reverting the instruction back to its original value, malicious code placed in memory will be randomly altered so that when it is executed by the processor it produces chaotic, random behavior that will not allow control of the processor to be compromised, eventually producing a processing error that will cause the processor to either shut down the software process where the code exists to reload, or reset.

Abstract: A method for changing a processor instruction randomly, covertly, and uniquely, so that the reverse process can restore it faithfully to its original form, making it virtually impossible for a malicious user to know how the bits are changed, preventing them from using a buffer overflow attack to write code with the same processor instruction changes into said processor's memory with the goal of taking control of the processor. When the changes are reversed prior to the instruction being executed, reverting the instruction back to its original value, malicious code placed in memory will be randomly altered so that when it is executed by the processor it produces chaotic, random behavior that will not allow control of the processor to be compromised, eventually producing a processing error that will cause the processor to either shut down the software process where the code exists to reload, or reset.

Abstract: A method for changing a processor instruction randomly, covertly, and uniquely, so that the reverse process can restore it faithfully to its original form, making it virtually impossible for a malicious user to know how the bits are changed, preventing them from using a buffer overflow attack to write code with the same processor instruction changes into said processor's memory with the goal of taking control of the processor. When the changes are reversed prior to the instruction being executed, reverting the instruction back to its original value, malicious code placed in memory will be randomly altered so that when it is executed by the processor it produces chaotic, random behavior that will not allow control of the processor to be compromised, eventually producing a processing error that will cause the processor to either shut down the software process where the code exists to reload, or reset.

Abstract: A secure or insecure communications channel for a secure communications system that carries sensitive user datagrams inside a proprietary or other undisclosed protocol so as to be able to encrypt the entire user datagram, including all header information so that if a malevolent entity were covertly or otherwise receiving said transmission they would be unable to determine the destination addresses of the user datagrams. Further the proprietary or undisclosed protocol is broken up into packets whose packet-to-packet boundaries are hidden so that malevolent entities will not be able to glean any information from the changes in traffic that occur during stimuli designed to provoke an expected response, thereby rendering said malevolent entities unable to determine what actual responses are occurring during real world events.

Abstract: A method for changing a processor instruction randomly, covertly, and uniquely, so that the reverse process can restore it faithfully to its original form, making it virtually impossible for a malicious user to know how the bits are changed, preventing them from using a buffer overflow attack to write code with the same processor instruction changes into said processor's memory with the goal of taking control of the processor. When the changes are reversed prior to the instruction being executed, reverting the instruction back to its original value, malicious code placed in memory will be randomly altered so that when it is executed by the processor it produces chaotic, random behavior that will not allow control of the processor to be compromised, eventually producing a processing error that will cause the processor to either shut down the software process where the code exists to reload, or reset.

Abstract: A secure or insecure communications channel for a secure communications system that carries sensitive user datagrams inside a proprietary or other undisclosed protocol so as to be able to encrypt the entire user datagram, including all header information so that if a malevolent entity were covertly or otherwise receiving said transmission they would be unable to determine the destination addresses of the user datagrams. Further the proprietary or undisclosed protocol is broken up into packets whose packet-to-packet boundaries are hidden so that malevolent entities will not be able to glean any information from the changes in traffic that occur during stimuli designed to provoke an expected response, thereby rendering said malevolent entities unable to determine what actual responses are occurring during real world events.

Abstract: A system and method for moving voice telephone calls through a data network. More particularly, the system and method are directed to the efficient operation of using identification numbers to route data packets through a communications node without reformatting individual data packets to the native protocol of that communications node. The exception is when the data packet will be more efficiently handled within the overall communications network by routing different pieces of that data packet to different outgoing port cards in a particular communications node, then the data packet will be reformatted, if necessary, to the native protocol of that communications node. The system and method allow the outgoing port card to convert the data packet into the correct format for transmission to either the destination (customer) or the next communications node. Together port cards and data switches form nodes. The port card receives and transmits out signals through respective ports connected to links between nodes.

Abstract: A method and system for improving the passage of silent or unused status of Ds0 channel to a data switch with a Ds0 switching capacity. The method allows the Ds0 channel source to be the only equipment that must engage a digital signal processor to remove silent and unused Ds0 channels from a Ds0 channel carrying data packet. The method provides for the Ds0 channel source, the intermediate nodes (data switches with Ds0 switching matrixes included) and Ds0 channel destination to recognize a simple and efficient means of passing suppression status of a Ds0 channel through the entire network.

Abstract: A method and system for improving the passage of silent or unused status of DsO channel to a data switch with a DsO switching capacity. The method allows the DsO channel source to be the only equipment that must engage a digital signal processor to remove silent and unused DsO channels from a DsO channel carrying data packet. The method provides for the DsO channel source, the intermediate nodes (data switches with DsO switching matrixes included) and DsO channel destination to recognize a simple and efficient means of passing suppression status of a DsO channel through the entire network.

Abstract: A system and method for moving voice telephone calls through a data network. More particularly, the system and method are directed to the efficient operation of a novel port card for installation in present and future versions of data switches. Together port cards and data switches form nodes. The port card receives and transmits out signals through respective ports connected to links between nodes. The method provides for voice data to be switched in a Ds0 switching matrix, which is resident on the port card.

Abstract: A method, apparatus, and computer program product of interfacing a time-domain multiplexed (TDM) link with a cell-switched network. The TDM link supports one or more active channels and one or more idle channels and supplies TDM frames with a sample of each channel in a dedicated timeslot. The TDM link is terminated at a first network node. One or more idle timeslots are removed from each TDM frame to create a compressed TDM frame, where each idle timeslot carries a sample of an idle channel. One or more compressed TDM frames are loaded in a cell that is sent over the cell-switched network to a second network node. The compressed TDM frames are unloaded from the cell. Idle timeslots are inserted in the compressed TDM frames to restore the compressed TDM frames to complete TDM frames. The bandwidth of the cell switched network is efficiently utilized because idle channel samples are not carried over the cell-switched network.

Abstract: A method and system for improving the passage of silent or unused status of Ds0 channel to a data switch with a Ds0 switching capacity. The method allows the Ds0 channel source to be the only equipment that must engage a digital signal processor to remove silent and unused Ds0 channels from a Ds0 channel carrying data packet. The method provides for the Ds0 channel source, the intermediate nodes (data switches with Ds0 switching matrixes included) and Ds0 channel destination to recognize a simple and efficient means of passing suppression status of a Ds0 channel through the entire network.

Abstract: An electrical box is provided for receiving an electrical unit. A low voltage section is configured to provide a low voltage connection, wherein a barrier isolates the low voltage connection. A high voltage section is separated from the low voltage section via the barrier to provide a high voltage connection. The high voltage section includes a plurality of bus bars, and a plurality of displacement connectors that are coupled to the plurality of bus bars and are configured redundantly to accept wires.

Abstract: An electrical box including a hollow container defining an interior space, as well as neutral and hot exterior connectors mounted on an exterior surface of the container, and ground, neutral, hot, and alternate hot interior conductive members mounted on an interior surface of the container which define a single circuit of the electrical box. The exterior connectors receive electrical power from a multi-conductor electrical cable and transfer the power to an electrical unit connected to the internal conductive members without the multi-conductor electrical cable entering the interior space of the electrical box. The exterior connectors are preferably insulation displacement connectors (IDCs) and are mounted to exterior bus bars that contain high current screw holes that, for alternative use, also accept high current wire connectors used where the electrical power is higher than the current capacity of the IDCs.

Abstract: An electrical unit including a body having a device surface and a mating surface. An electrical device configured to provide an electrical function to a user is arranged on the device surface, and neutral and hot contacts configured to receive respective neutral and hot conductive members of an electrical box are mounted on the mating surface. The electrical device may be any one of an outlet, a switch, circuit breaker, or any combination of these devices. In addition to the neutral and hot contacts, ground and alternative contacts may be provided on the mating surface and each contact may be a rigid electrical socket oriented in a keyed configuration so as to electrically connect to the respective conductive members without the use of connecting wires when the electrical unit is mated with the electrical box.

Abstract: A system and method for moving voice telephone calls through a data network. More particularly, the system and method are directed to the efficient operation of using identification numbers to route data packets through a communications node without reformatting individual data packets to the native protocol of that communications node. The exception is when the data packet will be more efficiently handled within the overall communications network by routing different pieces of that data packet to different outgoing port cards in a particular communications node, then the data packet will be reformatted, if necessary, to the native protocol of that communications node. The system and method allow the outgoing port card to convert the data packet into the correct format for transmission to either the destination (customer) or the next communications node. Together port cards and data switches form nodes. The port card receives and transmits out signals through respective ports connected to links between nodes.

Abstract: The present invention is directed to a method and system for unloading one or more T1 payloads from a target ATM cell where a target ATM cell has traveled over an ATM network that is emulating a T1 link. A plurality of ATM cells are stored in a cell buffer at a first rate. A buffer controller selects the target ATM cell from the bottom of the cell buffer. The buffer controller sends the T1 payloads carried in the target ATM cell to an elastic store buffer. The elastic buffer sends a plurality of timeslots in each T1 payload to a switch matrix at a second rate.