Abstract: A method and system of emulating a T1 link over an ATM network. A T1 line carrying a stream of T1 frames is terminated at a first ATM Data Terminating Equipment (DTE). T1 frames are loaded into ATM cells and sent over an ATM network to a second ATM DTE. The T1 frames are unloaded at the second ATM DTE, and sent to a switch matrix to be de-multiplexed. In one example of T1 emulation, two T1 payloads are inserted in each ATM cell payload. The corresponding T1 frame bits replace the two least significant bits in the VCI field of the ATM cell header. For quasi-fractional T1 emulation, three or four quasi-fractional T1 payloads can be carried in the ATM cell payload. For fractional T1 emulation, multiple fractional T1 payloads are carried in a fractional payload field, and a frame bit field is created in the ATM cell payload to carry the T1 frame bits. The use of a T1 framer at the second DTE is avoided by insuring the T1 frame bit positions are constant over successive ATM cells.

Abstract: A method and system for processing a High level Data Link Control (HDLC) message despite the occurrence of a frame slip event in an Asynchronous Transfer Mode (ATM) receiver avoiding re-transmission of an HDLC message when a frame slip event occurs during reception of an HDLC message. In one embodiment, an ATM receiver receives an ATM cell, where the ATM cell carries one or more T1 payloads. Each T1 payload contains a plurality of timeslots, including an HDLC timeslot. The HDLC timeslot is read for each T1 payload prior to unloading each T1 payload from the ATM cell. The plurality of timeslots within each T1 payload are sent to a switch matrix, where the timeslots are de-multiplexed. The HDLC message is carried in the HDLC timeslot over a plurality of ATM cells and the HDLC message is processed despite the occurrence of a frame slip event.