Patents by Inventor Frédéric Schumacher
Frédéric Schumacher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10725950Abstract: A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.Type: GrantFiled: September 24, 2018Date of Patent: July 28, 2020Assignee: Atmel CorporationInventors: Frédéric Schumacher, Guillaume Pean, Renaud Tiennot
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Patent number: 10437516Abstract: A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor.Type: GrantFiled: February 1, 2018Date of Patent: October 8, 2019Assignee: Atmel CorporationInventors: Frédéric Schumacher, Guillaume Pean, Renaud Tiennot
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Publication number: 20190026241Abstract: A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.Type: ApplicationFiled: September 24, 2018Publication date: January 24, 2019Inventors: Frédéric SCHUMACHER, Guillaume PEAN, Renaud TIENNOT
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Patent number: 10083137Abstract: A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.Type: GrantFiled: April 2, 2015Date of Patent: September 25, 2018Assignee: Atmel CorporationInventors: Frédéric Schumacher, Guillaume Pean, Renaud Tiennot
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Publication number: 20180157443Abstract: A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor.Type: ApplicationFiled: February 1, 2018Publication date: June 7, 2018Inventors: Frédéric Schumacher, Guillaume Pean, Renaud Tiennot
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Patent number: 9921778Abstract: A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor.Type: GrantFiled: April 7, 2016Date of Patent: March 20, 2018Assignee: Atmel CorporationInventors: Frédéric Schumacher, Guillaume Pean, Renaud Tiennot
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Publication number: 20160292109Abstract: A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.Type: ApplicationFiled: April 2, 2015Publication date: October 6, 2016Inventors: Frédéric SCHUMACHER, Guillaume PEAN, Renaud TIENNOT
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Publication number: 20160216917Abstract: A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor.Type: ApplicationFiled: April 7, 2016Publication date: July 28, 2016Inventors: Frédéric Schumacher, Guillaume Pean, Renaud Tiennot
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Patent number: 9329782Abstract: A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor.Type: GrantFiled: October 3, 2014Date of Patent: May 3, 2016Assignee: Atmel CorporationInventors: Frédéric Schumacher, Guillaume Pean, Renaud Tiennot
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Publication number: 20150149707Abstract: A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor.Type: ApplicationFiled: October 3, 2014Publication date: May 28, 2015Inventors: Frédéric Schumacher, Guillaume Pean, Renaud Tiennot
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Patent number: 8880785Abstract: A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor.Type: GrantFiled: September 28, 2012Date of Patent: November 4, 2014Assignee: Atmel CorporationInventors: Frédéric Schumacher, Guillaume Pean, Renaud Tiennot
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Patent number: 8805906Abstract: A variable architecture for random number generators is disclosed. In some implementations, the architecture of a random number generator may be varied based on microcontroller-specific data stored on the microcontroller. For example, a random number generator module may be embedded in a microcontroller circuit. The random number generator module may be designed to receive input from data sources in the circuit that contain microcontroller-specific data (e.g., a unique chip identifier, data carried in fuse bits). In some implementations, the architecture of the random number generator module may be adjusted or varied based on the microcontroller-specific data.Type: GrantFiled: March 9, 2011Date of Patent: August 12, 2014Assignee: Atmel CorporationInventors: Alain Vergnes, Guillaume Pean, Frederic Schumacher
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Publication number: 20140095764Abstract: A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: Atmel CorporationInventors: Frédéric Schumacher, Guillaume Pean, Renaud Tiennot
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Patent number: 8484436Abstract: A memory controller is configured to receive read requests from a processor and return memory words from memory. The memory controller comprises an address comparator and a loop entry cache. The address comparator is configured to determine a difference between a previous read request address and a current read request address. The address comparator is also configured to determine whether the difference is positive and less than a certain address difference and, if so, indicate a limited backwards jump. The loop entry cache is configured to store a current memory word for the current read request address when the address comparator indicates a limited backwards jump.Type: GrantFiled: September 2, 2010Date of Patent: July 9, 2013Assignee: Atmel CorporationInventors: Franck Lunadier, Frédéric Schumacher
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Publication number: 20120233232Abstract: A variable architecture for random number generators is disclosed. In some implementations, the architecture of a random number generator may be varied based on microcontroller-specific data stored on the microcontroller. For example, a random number generator module may be embedded in a microcontroller circuit. The random number generator module may be designed to receive input from data sources in the circuit that contain microcontroller-specific data (e.g., a unique chip identifier, data carried in fuse bits). In some implementations, the architecture of the random number generator module may be adjusted or varied based on the microcontroller-specific data.Type: ApplicationFiled: March 9, 2011Publication date: September 13, 2012Applicant: ATMEL ROUSSET S.A.S.Inventors: Alain Vergnes, Guillaume Pean, Frédéric Schumacher
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Publication number: 20120059975Abstract: A memory controller is configured to receive read requests from a processor and return memory words from memory. The memory controller comprises an address comparator and a loop entry cache. The address comparator is configured to determine a difference between a previous read request address and a current read request address. The address comparator is also configured to determine whether the difference is positive and less than a certain address difference and, if so, indicate a limited backwards jump. The loop entry cache is configured to store a current memory word for the current read request address when the address comparator indicates a limited backwards jump.Type: ApplicationFiled: September 2, 2010Publication date: March 8, 2012Applicant: ATMEL ROUSSET S.A.S.Inventors: Franck Lunadier, Frédéric Schumacher
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Patent number: 8131789Abstract: True random number generation circuitry utilizes a pair of oscillators driving a pair of linear feedback shift registers, with their output being combined to generate random numbers. At least one of the oscillators is programmable with a variable frequency. One embodiment controls the variable frequency of oscillators with output from one or more sets of oscillators and linear feedback shift registers. In other embodiments, linear feedback shift register output is captured and used to control the frequency of oscillators.Type: GrantFiled: March 28, 2008Date of Patent: March 6, 2012Assignee: Atmel CorporationInventors: Alain Vergnes, Frederic Schumacher
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Patent number: 7701802Abstract: A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to realize said first delay altered by the fraction number of delay elements.Type: GrantFiled: October 3, 2008Date of Patent: April 20, 2010Assignee: Atmel CorporationInventors: Alain Vergnes, Eric Matullk, Frederic Schumacher
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Patent number: 7679987Abstract: A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2× clock signal.Type: GrantFiled: September 9, 2008Date of Patent: March 16, 2010Assignee: Atmel CorporationInventors: Alain Vergnes, Eric Matulik, Frederic Schumacher
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Publication number: 20090248771Abstract: True random number generation circuitry utilizes a pair of oscillators driving a pair of linear feedback shift registers, with their output being combined to generate random numbers. At least one of the oscillators is programmable with a variable frequency. One embodiment controls the variable frequency of oscillators with output from one or more sets of oscillators and linear feedback shift registers. In other embodiments, linear feedback shift register output is captured and used to control the frequency of oscillators.Type: ApplicationFiled: March 28, 2008Publication date: October 1, 2009Applicant: ATMEL CORPORATIONInventors: Alain Vergnes, Frederic Schumacher