Abstract: Various embodiments include method and apparatus for receiving a clock signal, determining a number of delay elements based on a relationship between the clock signal and a delayed feedback signal generated based on the clock signal, calculating an amount of time corresponding to the number of delay elements, and delaying a control signal by the amount of time to generate an additional clock signal, the control signal having a frequency higher than a frequency of the clock signal. Other embodiments are described.

Abstract: Various apparatus and methods include a clock circuit to receive a first clock signal to generate a second clock signal having a frequency different from a frequency of the first clock signal. A clock capturing circuit receives the second clock signal for determining a number of delay elements corresponding to an amount of a period of the second clock signal. A delay calculation circuit calculates an amount of time corresponding to the number of delay elements. And a delay circuit delays an input control signal by the amount of time provided by the delay calculation circuit.

Abstract: A circuit for delaying an input control signal, comprises a clock circuit to generate a clock signal having a frequency different from an input clock signal to delay and including a clock signal input, a derivative clock signal output, an input to program a frequency ratio between its input clock frequency and its output clock frequency. A clock capturing circuit provides a determined number of delay elements required to provide a delay of an amount of the period of the signal provided by the clock circuit. A delay calculation circuit receives the determined number of delay elements and calculates a number of delay elements needed to delay the input control signal by an amount of time. A delay circuit includes a control signal input, a select input for receiving the number of delay elements provided by the delay calculation circuit.

Abstract: A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to realize said first delay altered by the fraction number of delay elements.

Abstract: A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2× clock signal.

Abstract: A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to realize said first delay altered by the fraction number of delay elements.

Abstract: A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2X clock signal.

Abstract: A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2× clock signal.

Abstract: A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to relaize said first delay altered by the fraction number of delay elements.

Abstract: A serial network controller contains control logic to analyze and determine a duration of a proper frame time slot. A number of data fields in a transmission is ascertained from an identifier field supplied in a header field. The number of data fields plus a margin for data framing overhead is calculated to determine the frame time slot duration. A timer is programmed with the calculated frame time slot duration. The timer is clocked at each bit period of the transmission until the calculated duration of the frame time slot is reached. At the frame time slot value, a transmit ready flag is unmasked, allowing termination of the frame with a proper margin. By managing frame time slot calculation, timer operations, and interrupt handling, the control logic relieves a microprocessor core and other system resources from network timing details. The control logic frees system resources for other applications.

Abstract: A serial network controller contains control logic to analyze and determine a duration of a proper frame time slot. A number of data fields in a transmission is ascertained from an identifier field supplied in a header field. The number of data fields plus a margin for data framing overhead is calculated to determine the frame time slot duration. A timer is programmed with the calculated frame time slot duration. The timer is clocked at each bit period of the transmission until the calculated duration of the frame time slot is reached. At the frame time slot value, a transmit ready flag is unmasked, allowing termination of the frame with a proper margin. By managing frame time slot calculation, timer operations, and interrupt handling, the control logic relieves a microprocessor core and other system resources from network timing details. The control logic frees system resources for other applications.