Abstract: Production of a device with superimposed levels of components including in this order: a) providing on a given level N1 provided with one or more components produced at least partially in a first semiconductor layer: a stack including a second semiconductor layer capable of receiving at least one transistor channel of level N2 above said given level N1, said stack including a so-called ground plane layer made of conductor or semiconductor material or doped semiconductor material situated between the first semiconductor layer and the second semiconductor layer as well as an insulator layer separating the ground plane layer from the second semiconductor layer, one or more islands being defined in the second semiconductor layer, b) forming a gate of a transistor on at least one island among said one or more islands, c) defining by etching distinct portions in the second semiconductor ground plane layer so as to free a space around at least one first etched portion of the ground plane layer arranged under an

Abstract: Method for producing a semiconductor substrate, including the implementation of the following steps: producing a superficial layer arranged on a buried dielectric layer and including a strained semiconductor region; producing an etching mask on the superficial layer, covering a part of the strained semiconductor region; etching the superficial layer according to a pattern of the etching mask, exposing at least one first lateral edge formed by a first strained semiconductor portion belonging to said part of the strained semiconductor region and which is in contact with the buried dielectric layer; modifying the first strained semiconductor portion into a second portion of material forming a mechanical support element arranged against the strained semiconductor region; removing the etching mask.

Abstract: An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.

Abstract: Production of a 3D microelectronic device including: assembling a structure comprising a lower level with a component partially formed in a first semiconductor layer with a support provided with a second semiconductor layer in which a transistor channel of an upper level is capable of being produced, the second semiconductor layer being capped with a dielectric material layer capable of forming a gate dielectric, forming a capping layer arranged on the dielectric material layer, and potentially capable of forming a lower gate portion of the transistor, defining a gate dielectric zone and an active zone of said transistor by etching the dielectric material layer and the second semiconductor layer, the capping layer protecting said dielectric material layer during this etching.

Abstract: An integrated circuit includes a substrate; a buried insulating layer; at least one nMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one pMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one semiconductor groundplane that may be doped or a metal, placed above the substrate and below the buried insulating layer, said buried plane being common to the nMOS transistor and to the pMOS transistor; at least one gate insulator and a gate that is common to the nMOS transistor and to the pMOS transistor and that is located above the channel of these transistors and facing the groundplane, the area of the groundplane at least covering the area of the gate in vertical projection; the nMOS transistor being separated from the pMOS transistor by an isolation defined between the semiconductor layer of the nMOS transistor and the semiconductor layer of the pMOS transistor, the isolation being located in the buried insulating l

Abstract: An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and second pMOS transistors including a channel that is subjected to compressive stress and made of an SiGe alloy, and a gate of said transistors being positioned at least 250 nm from a border of an active zone of said transistors; a third pair including a third nMOS transistor having a same construction as the first nMOS transistor and a third pMOS transistor having a same construction as the second pMOS transistor and exhibiting a compressive stress that is lower by at least 250 MPa, the gate of said transistors of the third pair being positioned at most 200 nm from the border.

Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.

Abstract: An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.

Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.

Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.

Abstract: Fabrication of a circuit with superposed transistors, comprising assembly of a structure comprising transistors formed from a first semiconducting layer with a support (100) provided with a second semiconducting layer (102) in which transistors are provided on a higher level (N2), the second semiconducting layer (102) being coated with a thin layer (101) of silicon oxide, the assembly of said structure and the support (100) being made by direct bonding in which the thin silicon oxide layer (101) is bonded to oxidised portions (37b, 37c) of getter material.

Abstract: Integrated circuit provided with several superimposed levels of transistors including: an upper level provided with transistors with a rear gate electrode laid out on a first semiconducting layer and a second semiconducting layer, a first transistor among said transistors of said upper level being provided with a contact pad traversing the second semiconducting layer, said contact pad being connected to a connection zone arranged between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line arranged on the side of a front face of the second semiconducting layer opposite to said rear face.

Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.

Abstract: An integrated circuit includes a substrate; a buried insulating layer; at least one nMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one pMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one semiconductor groundplane that may be doped or a metal, placed above the substrate and below the buried insulating layer, said buried plane being common to the nMOS transistor and to the pMOS transistor; at least one gate insulator and a gate that is common to the nMOS transistor and to the pMOS transistor and that is located above the channel of these transistors and facing the groundplane, the area of the groundplane at least covering the area of the gate in vertical projection; the nMOS transistor being separated from the pMOS transistor by an isolation defined between the semiconductor layer of the nMOS transistor and the semiconductor layer of the pMOS transistor, the isolation being located in the buried insulating l

Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.

Abstract: An integrated circuit comprising: first to third nMOS transistors with different threshold voltages, and first to third pMOS transistors with different threshold voltages, the nMOS transistors having channel regions made of silicon subjected to tensile stress and/or said pMOS transistors having channel regions made of SiGe subjected to compressive stress; a first well and a second well that are arranged underneath the nMOS transistors and underneath the pMOS transistors, respectively, with one and the same doping; two nMOS gate stacks comprising one and the same material, two of the nMOS gate stacks comprising materials having separate work functions, an nMOS gate stack having one and the same material as a pMOS gate stack, with the equation: Gp*Vdds?Gn*Gnds=Sn*|?n|+Sp*(|?p|?1.65*109)?VarCais+K.

Abstract: An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and second pMOS transistors including a channel that is subjected to compressive stress and made of an SiGe alloy, and a gate of said transistors being positioned at least 250 nm from a border of an active zone of said transistors; a third pair including a third nMOS transistor having a same construction as the first nMOS transistor and a third pMOS transistor having a same construction as the second pMOS transistor and exhibiting a compressive stress that is lower by at least 250 MPa, the gate of said transistors of the third pair being positioned at most 200 nm from the border.

Abstract: An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.

Abstract: An integrated circuit comprising: first to third nMOS transistors with different threshold voltages, and first to third pMOS transistors with different threshold voltages, the nMOS transistors having channel regions made of silicon subjected to tensile stress and/or said pMOS transistors having channel regions made of SiGe subjected to compressive stress; a first well and a second well that are arranged underneath the nMOS transistors and underneath the pMOS transistors, respectively, with one and the same doping; two nMOS gate stacks comprising one and the same material, two of the nMOS gate stacks comprising materials having separate work functions, an nMOS gate stack having one and the same material as a pMOS gate stack, with the equation: Gp*Vdds?Gn*Gnds=Sn*|?n|+Sp* (|?p|?1.65*109)?VarCais+K.

Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.