Patents by Inventor Francesco Pappalardo

Francesco Pappalardo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10566978
    Abstract: A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 18, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Francesco Pappalardo, Giuseppe Notarangelo
  • Patent number: 10547171
    Abstract: A power transistor supplying power to a load is coupled to a current limiter circuit including a differential amplifier that operates to detect a difference between a sense voltage, indicative of a load current, and a voltage reference. A control terminal of the power transistor is driven by a first output of the differential amplifier as a function of the detected difference. A voltage clamp circuit coupled to an input terminal generates a floating ground. A short-circuit protection circuit coupled to the floating ground and interposed between a second output of the differential amplifier and the control terminal of the power transistor provides a short-circuit protection for the first output of the differential amplifier. A reaction time circuit is coupled between the first and second outputs of the differential amplifier and a source terminal of the power transistor to limit a short-circuit current at the source terminal.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: January 28, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ignazio Bruno Mirabella, Francesco Pulvirenti, Salvatore Pappalardo
  • Publication number: 20190013813
    Abstract: A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.
    Type: Application
    Filed: August 20, 2018
    Publication date: January 10, 2019
    Inventors: Francesco Pappalardo, Giuseppe Notarangelo
  • Publication number: 20190011320
    Abstract: A capacitive sensor for monitoring stresses acting in a construction structure and having a multi-layer structure provided with an upper conductive layer defining an upper outer surface of the sensor. A lower conductive layer defines a lower outer surface. At least a first structural layer of insulating material is in contact with the upper conductive layer and at least a second structural layer of insulating material is in contact with the lower conductive layer. At least a first plate layer of conductive material and at least a second plate layer, of conductive material, and at least one dielectric layer is interposed between the first plate layer and the second plate layer to define at least one detection capacitor inside the multi-layer structure of the sensor. The upper and lower conductive layers jointly defining an electromagnetic screen for screening the detection capacitor against electromagnetic interference originating from outside the capacitive sensor.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 10, 2019
    Inventors: Francesco Pappalardo, Agatino Pennisi, Elio Guidetti, Angelo Doriani
  • Patent number: 10135733
    Abstract: A receiver circuit extracts data from a serial data signal. The serial data signal contains a data packet having a first format with a first number of bits or a second format with a second number of bits based on a selection signal. The second format comprises the bits of the first format followed by one or more additional bits. The receiver circuit has at least one shift register having a total number of bits equal or greater than the number of bits of the second format and a switching circuit that selectively connects the serial data signal to one of the shift register serial inputs as a function of the selection signal. When the first format is selected and the respective bits received, the bits are stored in given positions of the one or more shift registers. The switching circuit also, when the second format is selected and the respective bits received, stores the bits of the first format included at the beginning of the second format in the same given positions of the one or more shift registers.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: November 20, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Francesco Pappalardo, Giuseppe Notarangelo
  • Patent number: 10084455
    Abstract: A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: September 25, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Francesco Pappalardo, Giuseppe Notarangelo
  • Publication number: 20180159538
    Abstract: A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.
    Type: Application
    Filed: May 29, 2017
    Publication date: June 7, 2018
    Inventors: Francesco Pappalardo, Giuseppe Notarangelo
  • Publication number: 20180019946
    Abstract: A receiver circuit extracts data from a serial data signal. The serial data signal contains a data packet having a first format with a first number of bits or a second format with a second number of bits based on a selection signal. The second format comprises the bits of the first format followed by one or more additional bits. The receiver circuit has at least one shift register having a total number of bits equal or greater than the number of bits of the second format and a switching circuit that selectively connects the serial data signal to one of the shift register serial inputs as a function of the selection signal. When the first format is selected and the respective bits received, the bits are stored in given positions of the one or more shift registers. The switching circuit also, when the second format is selected and the respective bits received, stores the bits of the first format included at the beginning of the second format in the same given positions of the one or more shift registers.
    Type: Application
    Filed: October 25, 2016
    Publication date: January 18, 2018
    Inventors: Francesco Pappalardo, Giuseppe Notarangelo
  • Publication number: 20170248534
    Abstract: A monitoring device is for a block of building material. The monitoring device may include an electric supply line configured to be buried in the block of building material and having a flexible main cable, and flexible jumper cables coupled to the flexible main cable and extending outwardly. The monitoring device may include sensor devices configured to be buried in the block of building material and coupled to respective ones of the flexible jumper cables. Each sensor device may include a primary inductor coupled to the electric supply line at a position based upon peaks of a stationary waveform when the electric supply line is alternating current (AC) powered, and a monitoring circuit. The monitoring circuit may include an integrated sensor, and a secondary inductor magnetically coupled to the primary inductor and configured to supply the integrated sensor, and communicate through the electric supply line.
    Type: Application
    Filed: May 12, 2017
    Publication date: August 31, 2017
    Inventors: Giovanni GIRLANDO, Michele CALABRETTA, Francesco PAPPALARDO
  • Patent number: 9678027
    Abstract: A monitoring device is for a block of building material. The monitoring device may include an electric supply line configured to be buried in the block of building material and having a flexible main cable, and flexible jumper cables coupled to the flexible main cable and extending outwardly. The monitoring device may include sensor devices configured to be buried in the block of building material and coupled to respective ones of the flexible jumper cables. Each sensor device may include a primary inductor coupled to the electric supply line at a position based upon peaks of a stationary waveform when the electric supply line is alternating current (AC) powered, and a monitoring circuit. The monitoring circuit may include an integrated sensor, and a secondary inductor magnetically coupled to the primary inductor and configured to supply the integrated sensor, and communicate through the electric supply line.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 13, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Giovanni Girlando, Michele Calabretta, Francesco Pappalardo
  • Patent number: 9378077
    Abstract: Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: June 28, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Francesco Pappalardo, Giuseppe Notarangelo, Elio Guidetti
  • Publication number: 20150253268
    Abstract: A monitoring device is for a block of building material. The monitoring device may include an electric supply line configured to be buried in the block of building material and having a flexible main cable, and flexible jumper cables coupled to the flexible main cable and extending outwardly. The monitoring device may include sensor devices configured to be buried in the block of building material and coupled to respective ones of the flexible jumper cables. Each sensor device may include a primary inductor coupled to the electric supply line at a position based upon peaks of a stationary waveform when the electric supply line is alternating current (AC) powered, and a monitoring circuit. The monitoring circuit may include an integrated sensor, and a secondary inductor magnetically coupled to the primary inductor and configured to supply the integrated sensor, and communicate through the electric supply line.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 10, 2015
    Inventors: Giovanni Girlando, Michele Calabretta, Francesco Pappalardo
  • Patent number: 8817935
    Abstract: Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: August 26, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Visalli, Francesco Pappalardo
  • Patent number: 8250300
    Abstract: A cache memory system comprises a cache memory and a cache controller that receives a first address to access the cache memory. The cache controller includes a first address transformer receives the first address and to transform it into one first cache address; the first cache address is used for accessing the cache memory to retrieve a first part of a tag address portion. The cache controller includes a hit detector establishes an partial hit condition based on a comparison of the retrieved a first part of the tag address portion and a first predetermined part of the first address, and a second address transformer receives the first address and to transform it into one second cache address. The cache controller uses the one second cache address for accessing the cache memory to retrieve a data word in case the partial hit condition is established.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: August 21, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Visalli, Francesco Pappalardo
  • Patent number: 8126084
    Abstract: Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: February 28, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Visalli, Francesco Pappalardo
  • Patent number: 8078804
    Abstract: A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: December 13, 2011
    Assignees: STMicroelectronics S.r.l., STMicroelectronics N.V.
    Inventors: Francesco Pappalardo, Giuseppe Notarangelo, Elena Salurso, Elio Guidetti
  • Patent number: 8060725
    Abstract: A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) function. A load unit loads into the processor clusters data to be processed according to a same instruction. An intercluster data path exchanges data between the processor clusters. The intercluster data path is scalable to activate selected processor clusters. The processor operates simultaneously on SIMD, scalar and vectorial data.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: November 15, 2011
    Assignees: STMicroelectronics S.R.L., STMicroelectronics N.V.
    Inventors: Francesco Pappalardo, Giuseppe Notarangelo, Elena Salurso, Elio Guidetti
  • Patent number: 7991081
    Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: August 2, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Francesco Pappalardo, Giuseppe Notarangelo
  • Publication number: 20110060975
    Abstract: Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.
    Type: Application
    Filed: August 4, 2010
    Publication date: March 10, 2011
    Applicant: STMICROELECTRONICS s.r.l.
    Inventors: Francesco PAPPALARDO, Giuseppe Notarangelo, Elio Guidetti
  • Patent number: 7899860
    Abstract: A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: March 1, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Visalli, Francesco Pappalardo