Abstract: To execute the cell-search procedure in a cellular communication system (such as a system based upon the 3GPP TDD standard), there are available identification codes for the second step (slot synchronization) and for the third step (identification of the scrambling codes). The identification codes are identified by a process of correlation with the received signal and are used for obtaining from a correspondence table the parameters for the execution of the second step (CD) or of the third step (SCR). The correspondence table is stored in a reduced form by the identification, according to rules of symmetry and redundancy, of subtables designed to generate the entire table by appropriate combination operations. The search procedure in the correspondence table thus reduced is conveniently modified by the introduction of the combination operations. A preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95 or WBCDMA.

Abstract: Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.

Abstract: In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point real numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

Abstract: A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.

Abstract: A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) function. A load unit loads into the processor clusters data to be processed according to a same instruction. An intercluster data path exchanges data between the processor clusters. The intercluster data path is scalable to activate selected processor clusters. The processor operates simultaneously on SIMD, scalar and vectorial data.

Abstract: A data stream (b(t)) including high (“1”) and low (“0”) logical states is transmitted over an optical link by means of an optical source adapted to be driven via the data strema, to generate an optical signal for transmission over the optical link. The optical signal includes optical pulses generated at the occurrence of high logical states in the data stream b(t). The input data stream b(t) is coded into a coded data stream B(t) prior to the transmission over the optical link. The coding step minimizes the logical high states in the coded data stream, and the optical source is driven by means of the coded data stream wherein the number of logical high states has been minimized.

Abstract: To obtain frame synchronization and identify the cell codegroup in a cellular communication system (such as a system based upon the standard 3GPP FDD), there are available the synchronization codes organized in chips or letters transmitted at the beginning of respective slots. Slot synchronization is obtained previously in a first step of the operation of cell search. During a second step, there are acquired, by means of correlation or fast Hadamard transform, the energy values corresponding to the respective individual letters with reference to the possible starting positions of the corresponding frame within the respective slot. Operating in a serial way at the end of acquisition of the aforesaid energy values of the individual letters, or else operating in parallel, the energies of the corresponding words are determined. Of these energies only the maximum word-energy value and the information for the corresponding starting position are stored in a memory structure.

Abstract: Described herein is a method for parallel generating Walsh-Hadamard (WH) channelization codes and Orthogonal Variable Spreading Factor (OVSF) channelization codes, which are channelization codes formed by a plurality of strings of antipodal digits, each having a given length L and being identifiable by respective indices I formed by strings of binary digits, each having a given length N equal to the logarithm in base two of the length L of the channelization codes, the antipodal digits of the channelization codes assuming the values +1 and ?1 and the binary digits of said indices I assuming the values 0 and 1.

Abstract: A method is provided for using a reconfigurable control structure that includes a hard-wired control unit configured to execute a pre-defined instruction set and a programmable control unit configured to execute a programmable instruction set. The method includes associating with each of a plurality of instructions to be executed an operating code to be sent to both the hard-wired control unit and the programmable control unit. The operating code includes at least one bit identifying only one of either the hard-wired control unit or the programmable control unit. The identified control unit is designed to generate control signals for the instruction to be executed.

Abstract: Data are transmitted over a bus including a plurality of lines, wherein energy is dissipated as a result of data transmission. Preferably, the data to be transmitted in parallel are partitioned in a plurality of clusters of data bits. Each cluster is subject to re-ordering according to a set of reordering patterns to produce a corresponding set of respective candidate clusters of data bits. Crosstalk activity values related to transmitting the various candidate clusters are calculated and compared to identify an optimum cluster of data bits that minimizes the energy dissipated as a result of transmission by jointly minimizing the switching activity and the crosstalk activity. The optimum cluster of data bits so identified is then used for transmission over the bus. The optimum cluster of data bits thus causes those bits that give rise to high crosstalk activity to be allotted to bus lines having lower crosstalk capacitance values.

Abstract: Data are transmitted over a bus including a plurality of lines, wherein energy is dissipated as a result of data transmission. Preferably, the data to be transmitted in parallel are partitioned in a plurality of clusters of data bits. Each cluster is subject to re-ordering according to a set of reordering patterns to produce a corresponding set of respective candidate clusters of data bits. Crosstalk activity values related to transmitting the various candidate clusters are calculated and compared to identify an optimum cluster of data bits that minimizes the energy dissipated as a result of transmission by jointly minimizing the switching activity and the crosstalk activity. The optimum cluster of data bits so identified is then used for transmission over the bus. The optimum cluster of data bits thus causes those bits that give rise to high crosstalk activity to be allotted to bus lines having lower crosstalk capacitance values.

Abstract: A reconfigurable control structure for CPUs comprises a first control unit with a first basic instruction set associated therewith, and a second control unit, with a second instruction set associated therewith. Associated with the second control unit is at least one programming element for rendering the second instruction set selectively modifiable. Also present is at least one circuit element for supplying instruction codes to be executed to the first control unit and to the second control unit, so that each instruction can be executed under the control of at least one between the first control unit or the second control unit according to whether the instruction is comprised in the first basic instruction set and/or in the second selectively modifiable instruction set.

Abstract: A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.

Abstract: A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.

Abstract: A cache memory system, comprising at least one cache memory and a cache memory controller. The at least one cache memory includes a plurality of storage locations, each one identified by a corresponding cache address and being adapted to store tag address portions and data words, each data word corresponding to a respective tag address portion. The cache memory controller is adapted to receive a first address and to access the at least one cache memory based on the received first address. The cache memory controller includes a first address transformer adapted to receive the first address and to transform it into at least one first cache address corresponding thereto by applying a first transform function; the at least one first cache address is used by the cache memory controller for accessing the at least one cache memory to retrieve at least a first part of a tag address portion stored in at least one of the storage locations.

Abstract: A pipeline structure is provided for use in a digital system. The pipeline structure includes stages arranged in a sequence from a first stage for receiving an input of the pipeline structure to a last stage for providing an output of the pipeline structure. At least one intermediate stage is interposed between the first stage and the last stage. The pipeline structure also includes a phase shifting circuit for generating at least one local clock signal for controlling the at least one intermediate stage. The first stage and the last stage are controlled by a main clock signal, the at least one local clock signal is generated from the main clock signal, and the main clock signal and the at least one local clock signal are out of phase. Also provided is a method of operating a pipeline structure that includes stages arranged in a sequence.

Abstract: An image generating pipeline (IGP) includes a digital signal processor for implementing processing blocks connected in cascade for processing an input image that includes an array of raw pixel values to generated a color image that includes an array of reconstructed pixel values. A memory is coupled to the digital signal processor for storing the raw pixel values and the array of reconstructed pixel values. The digital signal processor includes a data cache, and the raw pixel values of the input image are processed through the processing blocks in sub-arrays having fractional dimensions of the pixel-dimensions of the whole image array. The sub-arrays include an input sub-array of pixel values being loaded from the memory for defining a working window.

Abstract: Once slot synchronization has been obtained in a first step, during a second step there is acquired, by means of correlation of the received signal (r) with the synchronization codes, the information corresponding to the codegroup and to the fine slot synchronization. The synchronization codes are split into codesets. In a first step, a synchronization code identifying a corresponding codeset (CS) is identified by means of correlation and search for the maximum value of correlation energy. In a second step, the received signal (r) is correlated with the remaining codes belonging to the codeset identified. The information thus obtained, which corresponds to all the synchronization codes comprised in the codeset identified, is used for obtaining frame synchronization and codegroup identification. Preferential application is in mobile communication systems based upon standards, such as UMTS, CDMA2000, IS95 or WBCDMA.

Abstract: A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.

Abstract: A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.