Abstract: In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.

Abstract: A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.

Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.

Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.

Abstract: In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.

Abstract: A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.

Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.

Abstract: A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.

Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.

Abstract: A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.

Abstract: A dead-time circuit includes a signal propagation path from a first input node receiving a PWM modulated control signal to an output node, such signal propagation path switchable between a non-conductive state and a conductive state, such that the signal at the first input node is transferred to the output node when the signal propagation path is in the conductive state. The dead-time circuit further includes a differentiator circuit block coupled to a second input node and to the signal propagation path, the second input node configured to be coupled to an intermediate node of a half-bridge circuit. The differentiator circuit block switches the signal propagation path between the non-conductive state and the conductive state as a function of a time derivative of a signal at the second input node. At least one time-delay circuit component delays transfer of the signal at the first input node to the output node.

Abstract: A power transistor supplying power to a load is coupled to a current limiter circuit including a differential amplifier that operates to detect a difference between a sense voltage, indicative of a load current, and a voltage reference. A control terminal of the power transistor is driven by a first output of the differential amplifier as a function of the detected difference. A voltage clamp circuit coupled to an input terminal generates a floating ground. A short-circuit protection circuit coupled to the floating ground and interposed between a second output of the differential amplifier and the control terminal of the power transistor provides a short-circuit protection for the first output of the differential amplifier. A reaction time circuit is coupled between the first and second outputs of the differential amplifier and a source terminal of the power transistor to limit a short-circuit current at the source terminal.

Abstract: A dead-time circuit includes a signal propagation path from a first input node receiving a PWM modulated control signal to an output node, such signal propagation path switchable between a non-conductive state and a conductive state, such that the signal at the first input node is transferred to the output node when the signal propagation path is in the conductive state. The dead-time circuit further includes a differentiator circuit block coupled to a second input node and to the signal propagation path, the second input node configured to be coupled to an intermediate node of a half-bridge circuit. The differentiator circuit block switches the signal propagation path between the non-conductive state and the conductive state as a function of a time derivative of a signal at the second input node. At least one time-delay circuit component delays transfer of the signal at the first input node to the output node.

Abstract: A circuit with galvanic isolation includes a series of n cascaded transformers including a first transformer and a last transformer in the series. A transmitter is coupled to the primary winding of the first transformer in the series of cascaded transformers, the transmitter being configured for supplying to the primary winding a transmission signal as a function of an input signal. A receiver is coupled to the secondary winding of the last transformer of the series of cascaded transformers and is configured for receiving at the secondary winding a reception signal transmitted over the series of cascaded transformers. A predistortion module is configured for applying to the transmission signal a predistortion including an (n?1)-fold integration, where n is the number of cascaded transformers, of a transmission signal that would be supplied to the input of a sole transformer present in a single-transformer solution.

Abstract: A circuit provides a high-voltage low-drop diode-like conductive path between a DC voltage supply terminal and a bootstrap terminal in charging a supply capacitor for driving a power switch with the capacitor set between the bootstrap terminal and an output terminal alternatively switchable between a low voltage and a high voltage DC voltage. In an embodiment, the circuit includes first and second transistors such as LDMOS depletion transistors with the first transistor set in a cascode arrangement between the bootstrap terminal and the DC voltage supply terminal and the second transistor coupled with a sense comparator for comparing the voltage at the bootstrap terminal with the voltage at said DC voltage supply terminal. The first and second transistors have common control terminals coupled with the DC voltage supply terminal and common coupling terminals to the bootstrap terminal.

Abstract: A power transistor supplying power to a load is coupled to a current limiter circuit including a differential amplifier that operates to detect a difference between a sense voltage, indicative of a load current, and a voltage reference. A control terminal of the power transistor is driven by a first output of the differential amplifier as a function of the detected difference. A voltage clamp circuit coupled to an input terminal generates a floating ground. A short-circuit protection circuit coupled to the floating ground and interposed between a second output of the differential amplifier and the control terminal of the power transistor provides a short-circuit protection for the first output of the differential amplifier. A reaction time circuit is coupled between the first and second outputs of the differential amplifier and a source terminal of the power transistor to limit a short-circuit current at the source terminal.

Abstract: A circuit with galvanic isolation includes a series of n cascaded transformers including a first transformer and a last transformer in the series. A transmitter is coupled to the primary winding of the first transformer in the series of cascaded transformers, the transmitter being configured for supplying to the primary winding a transmission signal as a function of an input signal. A receiver is coupled to the secondary winding of the last transformer of the series of cascaded transformers and is configured for receiving at the secondary winding a reception signal transmitted over the series of cascaded transformers. A predistortion module is configured for applying to the transmission signal a predistortion including an (n?1)-fold integration, where n is the number of cascaded transformers, of a transmission signal that would be supplied to the input of a sole transformer present in a single-transformer solution.

Abstract: A circuit provides a high-voltage low-drop diode-like conductive path between a DC voltage supply terminal and a bootstrap terminal in charging a supply capacitor for driving a power switch with the capacitor set between the bootstrap terminal and an output terminal alternatively switchable between a low voltage and a high voltage DC voltage. In an embodiment, the circuit includes first and second transistors such as LDMOS depletion transistors with the first transistor set in a cascode arrangement between the bootstrap terminal and the DC voltage supply terminal and the second transistor coupled with a sense comparator for comparing the voltage at the bootstrap terminal with the voltage at said DC voltage supply terminal. The first and second transistors have common control terminals coupled with the DC voltage supply terminal and common coupling terminals to the bootstrap terminal.

Abstract: A high voltage comparison circuit includes an input stage generating an intermediate signal as a result of a comparison between an input signal and a first voltage reference and an output stage configured to generate an output signal referenced to a second voltage reference (different from the first voltage reference) in response to the intermediate signal.

Abstract: A transceiver is connectable to a cable with at least three wires. The transceiver may include a controlled output stage including a high-side leg, having two P-type transistors coupled in series and having a common current terminal, coupled between an output pin and a positive supply pin. The P-type transistors have body regions coupled to the common current terminal of the high-side leg. A low-side leg, includes two N-type transistors coupled in series and having a common current terminal, coupled between the output pin and a negative supply pin. The N-type transistors have body regions coupled to the common current terminal of the low-side leg. The protection circuit also includes a voltage clamper coupled between the common current terminals.