Patents by Inventor Francimar Campana

Francimar Campana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6599574
    Abstract: The present invention relates to the deposition of dielectric layers, and more specifically to a method and apparatus for forming dielectric layers such as borophosphosilicate glass (BPSG) having improved film uniformity, higher deposition rate, superior gap fill/reflow capability, and smoother surface morphology. The method forms a dielectric layer with a process using helium carrier gas that produces substantially less downstream residue than conventional methods and apparatus, thereby reducing the need for chamber cleaning and increasing throughput of processed wafers. The present invention utilizes helium instead of nitrogen as carrier gas in a process for forming a dielectric layer such as BPSG to provide various unexpected benefits. According to one aspect, the present invention forms a dielectric film on a substrate, and prolongs a period between chamber cleanings in a system by using helium which produces substantially less downstream and upstream residue than a process using nitrogen.
    Type: Grant
    Filed: April 4, 1996
    Date of Patent: July 29, 2003
    Assignee: Applied Materials Inc.
    Inventors: Ellie Yieh, Paul Gee, Li-Qun Xia, Francimar Campana, Shankar Venkataranan, Dana Tribula, Bang Nguyen
  • Patent number: 6596343
    Abstract: A method for processing semiconductor substrates by reacting hydroxyl radicals with a precursor to cause the precursor to decompose and form a film which deposits on a substrate. Hydroxyl radicals, which are produced in a hydroxyl-ion producing apparatus outside of a chemical vapor deposition reactor, are mixed with a precursor to form a hydroxyl ions-precursor mixture. The hydroxyl ions-precursor mixture is introduced into the chemical vapor deposition reactor.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: July 22, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Himanshu Pokharna, Shankar Chandran, Srinivas D. Nemani, Chen-an Chen, Francimar Campana, Ellie Yieh, Li-Qun Xia
  • Patent number: 6537733
    Abstract: A method of forming a silicon carbide layer for use in integrated circuits is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a nitrogen source in the presence of an electric field. The as-deposited silicon carbide layer incorporates nitrogen therein from the nitrogen source.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: March 25, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Francimar Campana, Srinivas Nemani, Michael Chapin, Shankar Venkataraman
  • Patent number: 6521302
    Abstract: A method of reducing plasma-induced damage in a substrate, comprising providing a post-deposition ramp down of a plasma source power used in generating a plasma for substrate processing.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: February 18, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Francimar Campana-Schmitt, Carsten Schimanke
  • Publication number: 20020173169
    Abstract: A method for depositing a layer over a substrate includes depositing a first halogen-doped borophosphosilicate glass (BPSG) layer over said substrate at a first pressure level. A second halogen-doped BPSG layer is deposited over said first layer at a second pressure level, wherein said first pressure level is higher than said second pressure level.
    Type: Application
    Filed: April 10, 2001
    Publication date: November 21, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Francimar Campana, Li-Qun Xia, Ellie Yieh
  • Publication number: 20020119250
    Abstract: A method of forming a silicon carbide layer for use in integrated circuits is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a nitrogen source in the presence of an electric field. The as-deposited silicon carbide layer incorporates nitrogen therein from the nitrogen source.
    Type: Application
    Filed: February 23, 2001
    Publication date: August 29, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Francimar Campana, Srinivas Nemani, Michael Chapin, Shankar Venkataraman
  • Patent number: 6426015
    Abstract: A method is provided for reducing elevated boron concentrations (denoted as “boron spikes”) in an insulating layer containing silicon, boron and other elements where the layer interfaces with surfaces of a semiconductor device. The method includes the steps of: seasoning a reaction chamber by flowing into it a mixture of gasses containing silicon, boron, ozone and other elements in predetermined proportions under set conditions of time, pressure, temperature and flow rates to deposit on inner walls and surfaces of the chamber a thin seasoning coating, and placing a semiconductor device in the chamber and covering it with an insulating layer having a composition similar to the seasoning coating. Subsequent etching of selected portions of the insulating layer has been found not to expose conductive surfaces of the device.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: July 30, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Li-Qun Xia, Francimar Campana, Ellie Yieh
  • Patent number: 6261975
    Abstract: A method for improving the reflow characteristics of a BPSG film. According to the method, a fluorine- or other halogen-doped BPSG layer is deposited over a substrate and reflowed using a rapid thermal pulse (RTP) method. The use of such an RTP reflow method results in superior reflow characteristics as compared to a 20-40 minute conventional furnace reflow process. The inventors discovered that reflowing FBPSG films in a conventional furnace may result in the highly mobile fluorine atoms diffusing from the film prior to completion of the anneal. Thus, the FBPSG layer loses the improved reflow characteristics provided by the incorporation of fluorine into the film. The RTP reflow reflows the film in a minimal amount of time (e.g., 10-90 seconds depending on the temperature used to reflow the layer and the degree of planarization required among other factors).
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: July 17, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Li-Qun Xia, Francimar Campana, Ellie Yieh
  • Patent number: 6218268
    Abstract: A method for forming a BPSG film from a two-step deposition process and related apparatus and devices. A conformal layer of BPSG is deposited on a substrate. A more stable layer of BPSG is deposited at a higher deposition rate over the conformal layer. The method is suitable for filling trenches at least as narrow as 0.06 microns with aspect ratios of at least 5.5:1.
    Type: Grant
    Filed: May 5, 1998
    Date of Patent: April 17, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Li-Qun Xia, Ellie Yieh, Maria Galiano, Francimar Campana, Shankar Chandran
  • Patent number: 6153540
    Abstract: A method and apparatus for controlling the wet-etch rate and thickness uniformity of a dielectric layer, such as a phosphosilicate glass layer (PSG) layer. The method is based upon the discovery that the atmospheric pressure at which a PSG layer is deposited affects the wet-etch rate of the same, during a subsequent processing step, as well as the layer's thickness uniformity. As a result, the method of the present invention includes the step of pressurizing the atmospheric pressure of a semiconductor process chamber within a predetermined range after the substrate is deposited therein. Flowed into the deposition zone is a process gas comprising a silicon source, all oxygen source, and a phosphorous source; and maintaining the deposition zone at process conditions suitable for depositing a phosphosilicate glass layer on the substrate.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: November 28, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Ishing Lou, Cary Ching, Peter W. Lee, Rong Pan, Paul Gee, Francimar Campana
  • Patent number: 6090206
    Abstract: A throttle valve assembly is provided, including a throttle valve housing having a bore therethrough and a throttle valve plug assembly. The throttle valve plug assembly includes a shaft rotatably mounted on the throttle valve housing and a throttle valve plug having a concave cut-out portion. The throttle valve plug is mounted on the shaft within the throttle valve housing and substantially perpendicular to the bore. The throttle valve plug has at least two fully open positions and a closed position.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: July 18, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Won B. Bang, Matthew W. Losey, Francimar Campana, Srinivas Nemani, Sundar Pichai