Patents by Inventor Francisco Javier Santos Rodriguez

Francisco Javier Santos Rodriguez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11515264
    Abstract: A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: November 29, 2022
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
  • Publication number: 20220367191
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11502190
    Abstract: A vertical power semiconductor device is described. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface. A thickness of the semiconductor body between the first main surface and the second main surface ranges from 40 ?m to 200 ?m. Active device elements are formed in the semiconductor body at the first main surface. Edge termination elements at least partly surround the active device elements at the first main surface. A diffusion region extends into the semiconductor body from the second main surface. A doping concentration profile of the diffusion region decreases from a peak concentration Ns at the second main surface to a concentration Ns/e, e being Euler's number, over a vertical distance ranging from 1 ?m to 5 ?m.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: November 15, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Andre Brockmeier, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20220359428
    Abstract: A method for processing a semiconductor wafer is proposed. The method may include: reducing a thickness of the semiconductor wafer; before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer; and after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
  • Publication number: 20220359194
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Iris MODER, Bernhard GOLLER, Tobias Franz Wolfgang HOECHBAUER, Roland RUPP, Francisco Javier SANTOS RODRIGUEZ, Hans-Joachim SCHULZE
  • Patent number: 11476111
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 18, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Iris Moder, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Roland Rupp, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20220293558
    Abstract: A method for forming semiconductor devices includes: attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices; forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure; and reducing a thickness of the wide band-gap semiconductor wafer after attaching the glass structure. Additional methods for forming semiconductor devices are described.
    Type: Application
    Filed: June 1, 2022
    Publication date: September 15, 2022
    Inventors: Roland Rupp, Alexander Breymesser, Andre Brockmeier, Carsten von Koblinski, Francisco Javier Santos Rodriguez, Ronny Kern
  • Patent number: 11417528
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 16, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Publication number: 20220246745
    Abstract: A silicon carbide device includes a semiconductor substrate comprising a body region and transistor cell that comprises a source region, and a titanium carbide field electrode of the transistor cell, wherein the titanium carbide field electrode is connected to a reference voltage metallization structure or connectable to the reference voltage metallization structure by a switching device, wherein the reference voltage metallization is connected to a fixed voltage that is independent from a gate voltage of the transistor cell.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: Ralf Siemieniec, Thomas Aichinger, Iris Moder, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Carsten von Koblinski
  • Patent number: 11393784
    Abstract: A method for forming semiconductor devices includes attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices. The method further includes forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Alexander Breymesser, Andre Brockmeier, Carsten von Koblinski, Francisco Javier Santos Rodriguez, Ronny Kern
  • Publication number: 20220208691
    Abstract: One or more semiconductor structures and/or methods for forming support structures for semiconductor structures are provided. A first porosification layer is formed over a semiconductor substrate. A first epitaxial layer is formed over the first porosification layer. A second porosification layer is formed from a first portion of the first epitaxial layer and a support structure is formed from a second portion of the first epitaxial layer.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Inventors: Francisco Javier SANTOS RODRIGUEZ, Markus HARFMANN
  • Patent number: 11342433
    Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 24, 2022
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Iris Moder, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Carsten von Koblinski
  • Patent number: 11329021
    Abstract: A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Fabian Craes, Barbara Eichinger, Martin Mischitz, Frederik Otto, Fabien Thion
  • Publication number: 20220132677
    Abstract: A method of forming a current measurement device includes providing a glass substrate having first and second substantially planar surfaces that are opposite one another, forming a plurality of through-vias in the glass substrate that each extend between the first and second substantially planar surfaces, and forming conductive tracks on the glass substrate that connect adjacent ones of the through-vias together. Forming the plurality of through-vias includes applying radiation to the glass substrate, and the conductive tracks and the through-vias collectively form a coil structure in the glass substrate.
    Type: Application
    Filed: October 28, 2020
    Publication date: April 28, 2022
    Inventors: Alexander Breymesser, Francisco Javier Santos Rodriguez, Klaus Sobe
  • Publication number: 20220085174
    Abstract: A method of manufacturing a semiconductor device includes: providing a silicon carbide substrate that includes device regions and a grid-shaped kerf region laterally separating the device regions; forming a mold structure on a backside surface of the grid-shaped kerf region; forming backside metal structures on a backside surface of the device regions; and separating the device regions, wherein parts of the mold structure form frame structures laterally surrounding the backside metal structures.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Inventors: Andre Brockmeier, Guenter Denifl, Ronny Kern, Michael Knabl, Matteo Piccin, Francisco Javier Santos Rodriguez
  • Patent number: 11251266
    Abstract: A power semiconductor device includes a semiconductor body having a drift region of a first conductivity type inside an active region. An edge termination region includes: a guard region of a second conductivity type at a front side of the semiconductor body and surrounding the active region; and a field plate trench structure extending vertically into the body from the front side and at least partially filled with a conductive material that is electrically connected with the guard region and insulated from the body external of the guard region. A first portion of the field plate trench structure at least partially extends into the guard region and is at least partially arranged below a metal layer arranged at the front side. A second portion of the field plate trench structure extends outside of the guard region and surrounds the active area, the metal layer not extending above the second portion.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: February 15, 2022
    Assignee: Infineon Technologies AG
    Inventors: Philip Christoph Brandt, Manfred Pfaffenlehner, Frank Dieter Pfirsch, Francisco Javier Santos Rodriguez, Steffen Schmidt, Frank Umbach
  • Publication number: 20220037165
    Abstract: A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050° C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.
    Type: Application
    Filed: July 28, 2021
    Publication date: February 3, 2022
    Inventors: Hans-Joachim Schulze, Alexander Breymesser, Bernhard Goller, Matthias Kuenle, Helmut Oefner, Francisco Javier Santos Rodriguez, Stephan Voss
  • Patent number: 11239384
    Abstract: A semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface. A barrier layer including least one of silicon carbide, a ternary nitride, and a ternary carbide is formed on the rear side surface.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: February 1, 2022
    Assignee: INFINEON TECHNOLOGIESAG
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11211459
    Abstract: An auxiliary carrier and a silicon carbide substrate are provided. The silicon carbide substrate includes an idle layer and a device layer between a main surface at a front side of the silicon carbide substrate and the idle layer. The device layer includes a plurality of laterally separated device regions. Each device region extends from the main surface to the idle layer. The auxiliary carrier is structurally connected with the silicon carbide substrate at the front side. The idle layer is removed. A mold structure is formed that fills a grid-shaped groove that laterally separates the device regions. The device regions are separated, and parts of the mold structure form frame structures laterally surrounding the device regions.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andre Brockmeier, Guenter Denifl, Ronny Kern, Michael Knabl, Matteo Piccin, Francisco Javier Santos Rodriguez
  • Publication number: 20210351077
    Abstract: A method for processing a wide band gap semiconductor wafer includes: depositing a support layer including semiconductor material at a back side of a wide band gap semiconductor wafer, the wide band gap semiconductor wafer having a band gap larger than the band gap of silicon; depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer; and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer comprising at least a part of the epitaxial layer, and a remaining wafer comprising the support layer.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Inventors: Francisco Javier Santos Rodriguez, Günter Denifl, Tobias Hoechbauer, Martin Huber, Wolfgang Lehnert, Roland Rupp, Hans-Joachim Schulze