Abstract: In a method of generating a microelectromechanical system, MEMS, device, a MEMS substrate including a movable element is provided. A glass cover member including a glass cover is formed by hot embossing. The glass cover member is bonded to the MEMS substrate so as to hermetically seal by the glass cover a cavity in which the movable element is arranged.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.

Abstract: A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.

Abstract: A semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface. A barrier layer including least one of silicon carbide, a ternary nitride, and a ternary carbide is formed on the rear side surface.

Abstract: A power semiconductor device includes an active cell region with a drift region, and IGBT cells at least partially arranged within the active cell region. Each IGBT cell includes at least one trench extending into the drift region along a vertical direction, an edge termination region surrounding the active cell region, and a transition region arranged between the active cell region and the edge termination region. The transition region has a width along a lateral direction from the active cell region towards the edge termination region. At least some of the IGBT cells are arranged within, or, respectively, extend into the transition region. An electrically floating barrier region of each IGBT cell is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells. The electrically floating barrier region does not extend into the transition region.

Abstract: A semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface. A barrier layer including least one of silicon carbide, a ternary nitride, and a ternary carbide is formed on the rear side surface.

Abstract: A method includes producing a bulk substrate and beveling an edge of the bulk substrate using an electrical discharge machining (EDM) process and/or an electrochemical discharge machining (ECDM) process.

Abstract: In various embodiments, a method for processing a wafer is provided. The method includes forming a layer stack, including a support layer and a useful layer and a sacrificial region between them, said sacrificial region having, vis-à-vis a processing fluid, a lower mechanical and/or chemical resistance than the support layer and than the useful layer. The support layer has a depression, which exposes the sacrificial region. The method further includes forming at least one channel in the exposed sacrificial region by means of the processing fluid. The channel connects the depression to an exterior of the layer stack.

Abstract: A wafer arrangement in accordance with various embodiments may include: a wafer; and a wafer support ring, wherein the wafer and the wafer support ring are configured to be releasably coupled to one another so that the wafer support ring can be uncoupled from the wafer without causing damage to the wafer or the wafer support ring.

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

Abstract: A wafer carrier comprises a first foil, a second foil, and a chamber between the first and the second foil. The first foil has a perforation and is used for carrying the wafer. The first and the second foil are connected to each other so as to form the chamber. The chamber is configured to be evacuated to form a vacuum in the chamber, the vacuum causes an underpressure at the perforation, the underpressure forms a carrying force to the wafer to be carried.

Abstract: A power semiconductor device includes a semiconductor body having a drift region of a first conductivity type inside an active region. An edge termination region includes: a guard region of a second conductivity type at a front side of the semiconductor body and surrounding the active region; and a field plate trench structure extending vertically into the body from the front side and at least partially filled with a conductive material that is electrically connected with the guard region and insulated from the body external of the guard region. A first portion of the field plate trench structure at least partially extends into the guard region and is at least partially arranged below a metal layer arranged at the front side. A second portion of the field plate trench structure extends outside of the guard region and surrounds the active area, the metal layer not extending above the second portion.

Abstract: A battery includes a first substrate having a first main surface, a second substrate made of a conducting material or semiconductor material, and a carrier of an insulating material. The carrier has a first and a second main surfaces, the second substrate being attached to the first main surface of the carrier. An opening is formed in the second main surface of the carrier to uncover a portion of a second main surface of the second substrate. The second main surface of the carrier is attached to the first substrate, thereby forming a cavity. The battery further includes an electrolyte disposed in the cavity.

Abstract: A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.

Abstract: According to various embodiments, a substrate carrier may include: a substrate-supporting region for supporting a substrate; wherein a first portion of the substrate-supporting region including a pore network of at least partially interconnected pores; wherein a second portion of the substrate-supporting region surrounds the first portion and includes a sealing member for providing a contact sealing; at least one evacuation port for creating a vacuum in the pore network, such that a substrate received over the substrate-supporting region is adhered by suction; and at least one valve configured to control a connection between the pore network and the at least one evacuation port, such that a vacuum can be maintained in the pore network; wherein the pore network includes a first pore characteristic in a first region and a second pore characteristic in a second region different from the first pore characteristic.

Abstract: In various embodiments, a method of processing a monocrystalline substrate is provided. The method may include severing the substrate along a main processing side into at least two monocrystalline substrate segments, and forming a micromechanical structure comprising at least one monocrystalline substrate segment of the at least two substrate segments.

Abstract: An auxiliary carrier and a silicon carbide substrate are provided. The silicon carbide substrate includes an idle layer and a device layer between a main surface at a front side of the silicon carbide substrate and the idle layer. The device layer includes a plurality of laterally separated device regions. Each device region extends from the main surface to the idle layer. The auxiliary carrier is structurally connected with the silicon carbide substrate at the front side. The idle layer is removed. A mold structure is formed that fills a grid-shaped groove that laterally separates the device regions. The device regions are separated, and parts of the mold structure form frame structures laterally surrounding the device regions.

Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization material over a semiconductor body; performing a heating process so as to form at least one region in the semiconductor body including a eutectic of the first metallization material and material of the semiconductor body; and depositing a second metallization material over the semiconductor body so as to contact the semiconductor body via the at least one region in the semiconductor body.

Abstract: A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.