Abstract: A process for the preparation of complexes containing 68Ga wherein a buffer formic acid/formate in the presence of compounds capable to sequester metal cations is used in the complexation reaction.

Abstract: A method of processing a semiconductor substrate is provided. The method may include forming a film over a first side of a semiconductor substrate, forming at least one separation region in the semiconductor substrate between a first region and a second region of the semiconductor substrate, arranging the semiconductor substrate on a breaking device, wherein the breaking device comprises a breaking edge, and wherein the semiconductor substrate is arranged with the film facing the breaking device and in at least one alignment position with the at least one separation region aligned with the breaking edge, and forcing the semiconductor substrate to bend the first region with respect to the second region over the breaking edge until the film separates between the breaking edge and the at least one separation region.

Abstract: A process for the preparation of complexes containing 68Ga wherein a buffer formic acid/formate in the presence of compounds capable to sequester metal cations is used in the complexion reaction.

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face. The second main face is the backside of the semiconductor chip. The second main face includes a first region and a second region. The second region is a peripheral region of the second main face and the level of the first region and the level of the second region are different. The first region may be filled with metal and may be planarized to the same level as the second region.

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract: Methods and apparatuses are provided where a parting agent is applied to at least one portion of a substrate. The at least one portion of the substrate is removed from a carrier.

Abstract: A process for the preparation of complexes containing 68Ga wherein a buffer formic acid/formate in the presence of compounds capable to sequester metal cations is used in the complexion reaction.

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face. The second main face is the backside of the semiconductor chip. The second main face includes a first region and a second region. The second region is a peripheral region of the second main face and the level of the first region and the level of the second region are different. The first region may be filled with metal and may be planarized to the same level as the second region.

Abstract: A semiconductor device and method. One embodiment provides a semiconductor substrate having a plurality of cut regions. A metal layer is located within a cut region. The metal layer includes a recess, the recess having a slit-like shape.

Abstract: A method for fabricating an integrated circuit including forming a first trench in a rear side of a semiconductor wafer, wherein the first trench has a depth extending partially through a thickness of the semiconductor wafer, coating the rear side with a layer of coating material, including filling the first trench with the coating material, and forming a second trench in a front side of the semiconductor wafer, wherein the second trench is aligned with and has a width less than a width of the first trench, and wherein the second trench has a depth extending at least through a remaining portion of the semiconductor wafer so as to be in communication with the coating material filling the first trench.

Abstract: A semiconductor device and method. One embodiment provides a semiconductor substrate having a plurality of cut regions. A metal layer is located within a cut region. The metal layer includes a recess, the recess having a slit-like shape.

Abstract: One aspect includes an electronic device including an integrated component with a substrate. An electrically conductive first layer region is arranged at the substrate, wherein the layer thickness of the first layer region is greater than 10 micrometers or greater than 50 micrometers.

Abstract: A method for fabricating an integrated circuit including forming a first trench in a rear side of a semiconductor wafer, wherein the first trench has a depth extending partially through a thickness of the semiconductor wafer, coating the rear side with a layer of coating material, including filling the first trench with the coating material, and forming a second trench in a front side of the semiconductor wafer, wherein the second trench is aligned with and has a width less than a width of the first trench, and wherein the second trench has a depth extending at least through a remaining portion of the semiconductor wafer so as to be in communication with the coating material filling the first trench.

Abstract: An explanation is given of, inter alia, an electronic device (10), comprising: an integrated component (12) with a substrate, an electrically conductive first layer region (14), arranged at the substrate, wherein the layer thickness of the first layer region is greater than 10 micrometres or greater than 50 micrometres.