Patents by Inventor Franco Motika

Franco Motika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10365132
    Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
  • Patent number: 10254336
    Abstract: Techniques relate to an interactive logic diagnostic process. A diagnostic iteration loop is performed. When a critical failure does not have the diagnostic resolution that meets a predefined diagnostic resolution, potential faults related to the critical failure are isolated. When the critical failure has a diagnostic resolution that meets the predefined diagnostic resolution, the diagnostic iteration loop ends. Path focused fault test patterns are applied to the device under test in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because a number of the potential faults related to the critical failure has decreased, and/or a size of a physical area of the potential faults related to the critical failure has decreased. The diagnostic iteration loop is returned to.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Gary W. Maier, Franco Motika, Phong T. Tran
  • Patent number: 10247776
    Abstract: Structurally assisted functional test and diagnostics include executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints. One or more built-in structural test support circuits of the device under test is applied to identify one or more likely causes of a failure identified at the one or more checkpoints. A portion of the functional execution sequence between a plurality of the checkpoints is iteratively invoked to progressively isolate the one or more likely causes of the failure as a most likely failure source in combination with one or more results from the one or more built-in structural test support circuits.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Publication number: 20190094297
    Abstract: An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Publication number: 20190094298
    Abstract: An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.
    Type: Application
    Filed: November 7, 2017
    Publication date: March 28, 2019
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Patent number: 10209306
    Abstract: A computer system verifies functional test patterns for diagnostics, characterization and manufacture testing. The system generates, by a system designer, verification sequences including initial trace traces selected from a verification sequence data to test system functional design. The system includes a trace module, an emulated pattern generator module, and a test pattern verification and debug module. The trace module adds custom information to the traces to generate modified traces and the system executes the verification sequences against a device to generate traces. The trace module further processes the modified traces by parsing the captured modified traces. The system verifies data integrity and summarizes statistics of the captured traces. The emulated pattern generator module generates emulated test patterns, which are based on the output of the trace module and have independent format streams compatible with a device test port.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Franco Motika, John D. Parker, Gerard M. Salem
  • Patent number: 10203371
    Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: February 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Franco Motika, John D. Parker, Gerard M. Salem
  • Patent number: 10169510
    Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Gary W. Maier, Franco Motika, Phong T. Tran
  • Publication number: 20180306610
    Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
  • Publication number: 20180252769
    Abstract: Techniques relate to an interactive logic diagnostic process. A diagnostic iteration loop is performed. When a critical failure does not have the diagnostic resolution that meets a predefined diagnostic resolution, potential faults related to the critical failure are isolated. When the critical failure has a diagnostic resolution that meets the predefined diagnostic resolution, the diagnostic iteration loop ends. Path focused fault test patterns are applied to the device under test in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because a number of the potential faults related to the critical failure has decreased, and/or a size of a physical area of the potential faults related to the critical failure has decreased. The diagnostic iteration loop is returned to.
    Type: Application
    Filed: May 3, 2018
    Publication date: September 6, 2018
    Inventors: Mary P. KUSKO, Gary W. MAIER, Franco MOTIKA, Phong T. TRAN
  • Publication number: 20180238962
    Abstract: Structurally assisted functional test and diagnostics include executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints. One or more built-in structural test support circuits of the device under test is applied to identify one or more likely causes of a failure identified at the one or more checkpoints. A portion of the functional execution sequence between a plurality of the checkpoints is iteratively invoked to progressively isolate the one or more likely causes of the failure as a most likely failure source in combination with one or more results from the one or more built-in structural test support circuits.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 23, 2018
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Publication number: 20180238964
    Abstract: Providing non-destructive recirculation test support in a device under test includes determining an initial latch allocation of a plurality of latches to form a plurality of self-test chains for the device under test. An optimized latch allocation to the self-test chains is determined based on a plurality of physical and logical grouping constraints. One or more of the latches are adjusted and reassigned between one or more of the self-test chains based on the optimized latch allocation. A recirculating feedback is coupled from an output of at least one of the self-test chains to a recirculation selector. A test input source is coupled to the recirculation selector, where the recirculation selector is operable to select between providing the test input source or the recirculating feedback to an input of the at least one of the self-test chains.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 23, 2018
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Patent number: 10024910
    Abstract: Techniques relate to an interactive logic diagnostic process. A diagnostic iteration loop is performed. When a critical failure does not have the diagnostic resolution that meets a predefined diagnostic resolution, potential faults related to the critical failure are isolated. When the critical failure has a diagnostic resolution that meets the predefined diagnostic resolution, the diagnostic iteration loop ends. Path focused fault test patterns are applied to the device under test in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because a number of the potential faults related to the critical failure has decreased, and/or a size of a physical area of the potential faults related to the critical failure has decreased. The diagnostic iteration loop is returned to.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: July 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Gary W. Maier, Franco Motika, Phong T. Tran
  • Publication number: 20180075170
    Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 15, 2018
    Inventors: Mary P. KUSKO, Gary W. MAIER, Franco MOTIKA, Phong T. TRAN
  • Publication number: 20180067162
    Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test.
    Type: Application
    Filed: November 10, 2017
    Publication date: March 8, 2018
    Inventors: Franco Motika, John D. Parker, Gerard M. Salem
  • Patent number: 9857422
    Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Franco Motika, John D. Parker, Gerard M. Salem
  • Publication number: 20170370988
    Abstract: Examples of techniques for burn-in testing of an individually personalized device configuration are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: retrieving the individually personalized device configuration; enabling a device to receive the individually personalized device configuration, wherein the device is one of a plurality of devices; and loading the individually personalized device configuration to the device that is enabled, wherein other devices of the plurality of devices are disabled from receiving the individually personalized device configuration.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventors: Franco Motika, Soungbum You
  • Patent number: 9852245
    Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Gary W. Maier, Franco Motika, Phong T. Tran
  • Publication number: 20170343601
    Abstract: Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.
    Type: Application
    Filed: May 27, 2016
    Publication date: November 30, 2017
    Inventors: Robert M. Casatuta, Mary P. Kusko, Gary W. Maier, Franco Motika, Phong T. Tran
  • Publication number: 20170261554
    Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test.
    Type: Application
    Filed: March 8, 2016
    Publication date: September 14, 2017
    Inventors: Franco Motika, John D. Parker, Gerard M. Salem