Patents by Inventor Franco Motika

Franco Motika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11112457
    Abstract: A series of pseudo-random test patterns provide inputs to a logic circuit for performing logic built-in self test (LBIST). A weight configuration module applies one or more weight sets to the pseudo-random test patterns, to generate a series of weighted pseudo-random test patterns. A logic analyzer determines a probability expression for each given net of the logic circuit, based on associated weight sets and a logic function performed by the net. A probability module computes an output probability for each net based on associated probability expressions and associated input probabilities. The weight configuration module optimizes the weight sets, based on the computed net probabilities, and further based on a target probability range bounded by lower and upper cutoff probabilities.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Mary P. Kusko, Franco Motika, Eugene Atwood
  • Publication number: 20210270898
    Abstract: Examples described herein provide a computer-implemented method that includes initiating a logic built-in self-test (LBIST) of a device under test (DUT). The method further includes performing latch state counting using a multiple input signature register (MISR) of the DUT, the performing responsive to the MISR being in a counter mode. The method further includes performing a latch transition counting of latches of the DUT using the MISR of the DUT and a storage latch, the performing responsive to the MISR being in the counter mode. The method further includes performing a latch count comparison by comparing an output of the MISR responsive to the MISR being in the counter mode to an output of a count compare register, the output of the count compare register representing a desired MISR state.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 2, 2021
    Inventors: Franco Motika, Richard Frank Rizzolo, Paul Jacob Logsdon
  • Patent number: 11105853
    Abstract: Examples described herein provide a computer-implemented method that includes initiating a logic built-in self-test (LBIST) of a device under test (DUT). The method further includes performing latch state counting using a multiple input signature register (MISR) of the DUT, the performing responsive to the MISR being in a counter mode. The method further includes performing a latch transition counting of latches of the DUT using the MISR of the DUT and a storage latch, the performing responsive to the MISR being in the counter mode. The method further includes performing a latch count comparison by comparing an output of the MISR responsive to the MISR being in the counter mode to an output of a count compare register, the output of the count compare register representing a desired MISR state.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Franco Motika, Richard Frank Rizzolo, Paul Jacob Logsdon
  • Patent number: 11079433
    Abstract: An approach for testing, including a self-test method, a semiconductor chip is disclosed. The approach generates test patterns, including weighted random test patterns, for testing random pattern resistant faults, and un-modeled faults directed at specific logic groups, where the dynamically generated test pattern weights are configured to optimize test coverage and test time. The dynamically generated test patterns are based on factors related to random pattern resistant logic structures interconnected via scan chains. More particularly, the dynamically generated test patterns are designed to enable fault detection within logic structures that are resistant to fault detection when tested with random patterns.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Franco Motika, Mary P. Kusko, Eugene Atwood
  • Publication number: 20210156911
    Abstract: An approach for testing, including a self-test method, a semiconductor chip is disclosed. The approach generates test patterns, including weighted random test patterns, for testing random pattern resistant faults, and un-modeled faults directed at specific logic groups, where the dynamically generated test pattern weights are configured to optimize test coverage and test time. The dynamically generated test patterns are based on factors related to random pattern resistant logic structures interconnected via scan chains. More particularly, the dynamically generated test patterns are designed to enable fault detection within logic structures that are resistant to fault detection when tested with random patterns.
    Type: Application
    Filed: November 25, 2019
    Publication date: May 27, 2021
    Inventors: Franco Motika, Mary P. Kusko, Eugene Atwood
  • Publication number: 20210156910
    Abstract: A series of pseudo-random test patterns provide inputs to a logic circuit for performing logic built-in self test (LBIST). A weight configuration module applies one or more weight sets to the pseudo-random test patterns, to generate a series of weighted pseudo-random test patterns. A logic analyzer determines a probability expression for each given net of the logic circuit, based on associated weight sets and a logic function performed by the net. A probability module computes an output probability for each net based on associated probability expressions and associated input probabilities. The weight configuration module optimizes the weight sets, based on the computed net probabilities, and further based on a target probability range bounded by lower and upper cutoff probabilities.
    Type: Application
    Filed: November 25, 2019
    Publication date: May 27, 2021
    Inventors: Mary P. Kusko, Franco Motika, Eugene Atwood
  • Patent number: 10930364
    Abstract: Methods, systems and computer program products for loading, storing and executing dynamically modifiable functional exercisers are provided. Aspects also include receiving a plurality of functional exercisers by a secondary reload memory disposed on a device-under-test. Aspects include loading at least a first functional exerciser from the secondary reload memory into a primary execution memory disposed on the device-under-test. Aspects include executing and modifying the first functional exerciser stored in the primary execution memory. Aspects further include, responsive to determining based on a test algorithm that one or more functional exercisers of the plurality have not been fully executed, loading a second functional exerciser from the secondary reload memory into the primary execution memory.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Franco Motika, Gerard Salem, Mary Kusko
  • Patent number: 10768230
    Abstract: Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert M. Casatuta, Mary P. Kusko, Gary W. Maier, Franco Motika, Phong T. Tran
  • Publication number: 20200160932
    Abstract: Methods, systems and computer program products for loading, storing and executing dynamically modifiable functional exercisers are provided. Aspects also include receiving a plurality of functional exercisers by a secondary reload memory disposed on a device-under-test. Aspects include loading at least a first functional exerciser from the secondary reload memory into a primary execution memory disposed on the device-under-test. Aspects include executing and modifying the first functional exerciser stored in the primary execution memory. Aspects further include, responsive to determining based on a test algorithm that one or more functional exercisers of the plurality have not been fully executed, loading a second functional exerciser from the secondary reload memory into the primary execution memory.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Franco Motika, Gerard Salem, Mary Kusko
  • Patent number: 10613142
    Abstract: Providing non-destructive recirculation test support in a device under test includes determining an initial latch allocation of a plurality of latches to form a plurality of self-test chains for the device under test. An optimized latch allocation to the self-test chains is determined based on a plurality of physical and logical grouping constraints. One or more of the latches are adjusted and reassigned between one or more of the self-test chains based on the optimized latch allocation. A recirculating feedback is coupled from an output of at least one of the self-test chains to a recirculation selector. A test input source is coupled to the recirculation selector, where the recirculation selector is operable to select between providing the test input source or the recirculating feedback to an input of the at least one of the self-test chains.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Patent number: 10598526
    Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
  • Patent number: 10585142
    Abstract: An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Patent number: 10571519
    Abstract: Embodiments include methods, and computer system, and computer program products for performing system functional test on a chip having partial-good portions. Aspects include: initializing, by system functional test software, a service engine of the chip, performing, by service engine, system functional test, and completing system functional test of chip. The chip may include service engine, a service engine memory and one or more “partial-good” portions. The initializing may include: loading system functional test software into the service engine memory, identifying each “partial-good” portion of the chip, writing a “partial-good” parameter for each “partial-good” portion of the chip identified to service engine memory, and triggering execution of system functional test. Method may include: decoding system functional test software, retrieving “partial-good” parameters, initializing “partial-good” portions of chip, and performing system functional test on “partial-good” portions of chip.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mitesh A. Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem
  • Patent number: 10545188
    Abstract: An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Patent number: 10365132
    Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
  • Patent number: 10254336
    Abstract: Techniques relate to an interactive logic diagnostic process. A diagnostic iteration loop is performed. When a critical failure does not have the diagnostic resolution that meets a predefined diagnostic resolution, potential faults related to the critical failure are isolated. When the critical failure has a diagnostic resolution that meets the predefined diagnostic resolution, the diagnostic iteration loop ends. Path focused fault test patterns are applied to the device under test in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because a number of the potential faults related to the critical failure has decreased, and/or a size of a physical area of the potential faults related to the critical failure has decreased. The diagnostic iteration loop is returned to.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Gary W. Maier, Franco Motika, Phong T. Tran
  • Patent number: 10247776
    Abstract: Structurally assisted functional test and diagnostics include executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints. One or more built-in structural test support circuits of the device under test is applied to identify one or more likely causes of a failure identified at the one or more checkpoints. A portion of the functional execution sequence between a plurality of the checkpoints is iteratively invoked to progressively isolate the one or more likely causes of the failure as a most likely failure source in combination with one or more results from the one or more built-in structural test support circuits.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Publication number: 20190094298
    Abstract: An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.
    Type: Application
    Filed: November 7, 2017
    Publication date: March 28, 2019
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Publication number: 20190094297
    Abstract: An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Patent number: 10209306
    Abstract: A computer system verifies functional test patterns for diagnostics, characterization and manufacture testing. The system generates, by a system designer, verification sequences including initial trace traces selected from a verification sequence data to test system functional design. The system includes a trace module, an emulated pattern generator module, and a test pattern verification and debug module. The trace module adds custom information to the traces to generate modified traces and the system executes the verification sequences against a device to generate traces. The trace module further processes the modified traces by parsing the captured modified traces. The system verifies data integrity and summarizes statistics of the captured traces. The emulated pattern generator module generates emulated test patterns, which are based on the output of the trace module and have independent format streams compatible with a device test port.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Franco Motika, John D. Parker, Gerard M. Salem