Abstract: A method of forming an optical disc, and an optical disc formed, so as to facilitate identifying unauthorized copies of the disc by using a defined procedure for reading the disc. The method comprises the steps of encoding digital data, comprised of a series of 0s and 1s, in the disc by forming a series of spaced pits along a track, so that the track comprises a series of pits and lands, and wherein, when said defined procedure is used to read the disc, each of said pits and lands is read as either a 0 or a 1. The method comprises the further step of forming at least one fuzzy area on the track so that when the defined procedure is used to read the disc, the fuzzy area is sometimes read as 0 and sometimes read as 1. With a preferred procedure, the pits reflect a given light beam at a first intensity, the lands reflect the given light at a second intensity, and the fuzzy area reflects the given light at a third intensity substantially midway between the first and second intensities.

Abstract: A method for testing external connections to semiconductor devices. The method includes providing an external electrical path between selected external connections on the semiconductor devices.

Abstract: An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns and grouping the multi-bit test patterns by a plurality of test pattern partitions including a first test pattern partition having a first number of bits and a second test pattern partition having second number of bits greater than the first number. The first test pattern partition is applied to the integrated circuit to generate a first signature that is compared to a first reference signature to detect a failure. The second test pattern partition is applied to the integrated circuit to generate a second signature that is compared to a second reference signature to detect a failure in the integrated circuit.

Abstract: Methods, data processing systems or program products which provide a user interface capable of inserting a reference marker at a point within an application window, causing a first representation of the reference marker to be displayed at that point and a second representation of the reference marker to be displayed in a scroll bar area within the application window which precisely corresponds to the location of the point. A pointing operation can be performed on the second representation of the reference marker causing the first representation of the reference marker along with the operating point to immediately appear within the application window. Additional reference markers may be inserted at additional points within the application window allowing the user to immediately find and display any point within the application window that the user has referenced with a reference marker.

Abstract: In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

Abstract: A structure for testing external connections to semiconductor devices. The structure includes an external electrical path between selected external connections on the semiconductor devices.

Abstract: For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated.

Abstract: A method is provided for a user to generate a password for a software application accessible from a computer system which includes a universal password generator (UPG). The UPG includes a specified parameter for generating the password, and the software application requires the password includes a specified parameter. The UPG is initiated and the universal password is inputted into the UPG. The specified parameter required by the application, and the UPG specified parameter are inputted into the UPG. The universal password is processed such that the specified parameter of the UPG, and the specified parameter of the application are used to generate the password. The password is then transferred to the application requiring the password. The password may be saved and associated in the UPG with the program such that when the user re-enters the program, the UPG program retrieves the password for reuse in the program.

Abstract: A method of diagnosing complex semiconductor device functional testing failures by combining deterministic and functional testing with diagnostic techniques. The method determines the failing logic locations by creating a new test pattern based on the functional failure by transforming a functional pattern into a scan deterministic pattern so that existing diagnostic tools can also be used to determine the location of and type of error in the failing circuit without impacting manufacturing test. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector.

Abstract: In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

Abstract: The present invention, enables complementing the state of either the master (L1) or slave latch (L2) in the shift register latches (SRLs) without changing the state of the other. When this is done after properly loading the LSSD scan chain using a normal scan chain sequence, the next system clock sequence can be used to launch a desired transition from each SRL in the scan chain. The actual mechanism for complementing the state of latches in LSSD scan chains can vary depending on which one of the L1 or L2 latch is being complemented; details of the actual scan chain and Shift Register Latch (SRL) design; and the semiconductor chip circuit technology. The complementing function can be provided as an integral part of the SRL design with minimal impact to system path and performance. An alternate complementing method would be to use a self complementing latch function.

Abstract: A system and method for adding a plug-in to a web browser, the system and method comprising providing a general functions list that lists at least one function that can be performed by at least one registered plug-in through the web browser, and selecting one function that a user would like to add to the web browser from the general functions list. In one preferred embodiment, the system and method further comprise generating a specific plug-ins list that lists at least one registered plug-in that can perform the selected function, and selecting one registered plug-in to perform the selected function from the specific plug-ins list. In one preferred embodiment, the system and method comprise the selecting of a registered plug-in from a general plug-ins list that lists at least one registered plug-in, and the providing of a specific functions list that lists every function that the selected registered plug-in can perform.

Abstract: Credit card or portable identification cards containing smart card technology and electronic fuse (e-fuse) technology are combined with an LFSR pseudo random number generator to provide a secured method to prevent fraud and unauthorized use. Secure personalization via e-fuses, a pseudo-random number generator linear feedback shift register, free running clock oscillator, and power source embedded in the card provide a highly secured method to render a lost or stolen card useless. A unique card ID is permanently encoded within the card which requires a specific activation code to activate the card. A PIN number permits the card owner to activate the card for a predetermined length of time while processing a transaction. The card dynamically generates random code sequences and synchronization keys to secure a transaction.

Abstract: A method and computer program capable of providing a plurality of activation areas in a display, the display having a plurality of selectable objects surrounded by an object area which defines the boundaries of the selectable objects which must be contacted by a pointing device for selection. The activation areas surround the selectable objects and expand the boundary of the selectable objects which must be contacted by the pointing device for selection. The size of the activation areas is determined by an expansion boundary having a border that outlines the size and shape of the activation areas and enlarges the activation areas to a maximum size without overlapping.

Abstract: LBIST and weighted LBIST tests are performed simultaneously on different portions of the tested object. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during test. It can be applied at wafer, chip, MCM, and system levels of test. Most importantly, it does not need new tools for support. Current test software will work as it does with the traditional test strategy. Scheduling the LBIST and weighted LBIST tests in the same test session reduces the overall power consumption because weighted LBIST testing consumes much less power than flat LBIST testing. In the same test session, if some parts of the logic is tested using weighted LBIST while the others were tested using LBIST, the power consumed by the circuit element at any given time is reduced.

Abstract: Test apparatus provides both flat pseudo random test patterns in combination with weighted pseudo random test patterns that the weight applied to every latch in the LSSD chain can be changed on every cycle. This apparatus fully integrates on-chip weighted pattern generation with either internal or external weight set selection. With WRP test technology, the WRP patterns are generated by the tester either externally or internally to the DUT and loaded via the shift register inputs (SRIs or WPIs) into the chip's shift register latches (SRLs). A test (or LSSD tester loop sequence) includes loading the SRLs in the SR chains with a WRP, pulsing the appropriate clocks, and unloading the responses captured in the SRLs into the multiple input signature register (MISR). Each test can then be applied multiple times for each weight set, with the weight-set assigning a weight factor or probability to each SRL.

Abstract: While data cannot be transmitted down a scan chain through a stuck-at fault location, data in properly operating latches downstream of the stuck-at fault location can be shifted down the chain. By varying an operating parameters such as power supply and reference voltages, clock timing patterns, temperature and timing sequences, one or more latches down the SRL chain from the stuck-at fault location may be triggered to change state from the stuck-at fault value. The SRL chain is then operated to shift data out the output of the SRL chain. The output is monitored and any change in value from the stuck-at state is noted as identifying all good latch positions to end of the chain. The process is repeated varying each of the selected operating parameters with the latch position following the stuck-at fault latch is identified.

Abstract: Logic scan based design and electronic fuse (e-fuse) technology are combined to create a circuit macro function that is integrated in a non-critical area of a processor chip or related circuit to provide a new means of securing electronic systems and devices such as computers, appliances, consumer electronics, automobiles, etc. from theft or unauthorized use. Level sensitive scan design (LSSD) techniques are used in conjunction with e-fuses to inhibit or enable system components and sub-components based upon a pre-initialized configuration which must be enabled by a user via password entry.

Abstract: Credit card or portable identification cards containing smart card technology and electronic fuse (e-fuse) technology are combined with a LFSR pseudo random number generator to provide a secured method to prevent fraud and unauthorized use. Secure personalization via e-fuses, a pseudo random number generator linear feedback shift register, free running clock oscillator, and power source embedded in the card enable a highly secured method to render a lost or stolen card useless. A unique card ID is permanently encoded within the card which requires a specific activation code to activate the card. A PIN number provides a means for the card owner to activate the card for a predetermined length of time while processing a transaction. The card's security generation function dynamically generates random code sequences and synchronization keys to secure a transaction.

Abstract: In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.