Abstract: A diagnostic process applicable to VLSI designs to address the accuracy of diagnostic resolution. Environmentally based fail data drives adaptive test methods which hone the test pattern set and fail data collection for successful diagnostic resolution. Environmentally based fail data is used in diagnostic simulation to achieve a more accurate environmentally based fault callout. When needed, additional information is included in the process to further refine and define the simulation or callout result. Similarly, as needed adaptive test pattern generation methods are employed to result in enhanced diagnostic resolution.

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: Methods, systems and program products for securely voting by providing a secure voting module in communication with a voting device. A voter signs onto the voting device using a unique voter identification, and the voter's voting selections are written to the voting device. A scrambled voter identification is generated using the unique voter identification and a unique encryption value of the secure voting module, whereby the voting selections and the scrambled voter identification are stored in the secure voting module. Once voting has ended, first and second fuses are blown within the secure voting module for destroying the unique encryption value and for permanently storing the voting selections and scrambled voter identification in a read only secure voting module that maintains voter anonymity while preventing any further physically writing thereto. The voting results may then be counted, re-counted or validated.

Abstract: Logic scan based design and electronic fuse (e-fuse) technology are combined to create a circuit macro function that is integrated in a non-critical area of a processor chip or related circuit to provide a new means of securing electronic systems and devices such as computers, appliances, consumer electronics, automobiles, etc. from theft or unauthorized use. Level sensitive scan design (LSSD) techniques are used in conjunction with e-fuses to inhibit or enable system components and sub-components based upon a pre-initialized configuration which must be enabled by a user via password entry.

Abstract: A diagnostic and characterization tool applicable to structural VLSI designs to address problems associated with fault tester interactive pattern generation and ways of effectively reducing diagnostic test time while achieving greater fail resolution. Empirical fail data drives the creation of adaptive test patterns which localize the fail to a precise location. This process iterates until the necessary localization is achieved. Both fail signatures and associated callouts as well as fail signatures and adaptive patterns are stored in a library to speed diagnostic resolution. The parallel tester application and adaptive test generation provide an efficient use of resources while reducing overall test and diagnostic time.

Abstract: A method for controlling access to data contained within a radio frequency identification (RFID) tag associated with an item includes reading the RFID tag; receiving a first value from a personal communication device associated with a purchaser of the item; creating a key using the first value received from the personal communication device and a second value associated with the item; and initially transmitting the key to both the RFID tag and the personal communication device. The RFID tag is configured to automatically program one or more electrically programmable fuse devices therein so as to prevent subsequent reading of data therein by an RFID reading device, upon receipt of a valid key initially transmitted thereto. The RFID tag is further configured to automatically program one or more additional fuse devices therein so as to restore read access to the data therein, upon receipt of a valid key subsequently transmitted thereto.

Abstract: In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

Abstract: A system for tracking the location of electronic devices and prohibiting unauthorized operation thereof includes a control unit, configured for wireless communication with an electronic device, the electronic device having a basic input/output system (BIOS) associated therewith. The control unit is configured to remotely disable the electronic device in the event the electronic device is detected to be beyond a programmed radius for a programmed duration, in accordance with a specifically defined level of security, wherein the extent to which the electronic device is disabled by the control unit is dependent upon the specifically defined level of security.

Abstract: A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of operations for the circuit.

Abstract: Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.

Abstract: The Nth state of an n-stage linear feedback shift register (LFSR) used to generate pseudo random binary sequences or patterns, and which may be configured as a multiple input signature register (MISR) or single input signature register (SISR) to compress data and generate signatures, is determined by building a look-up table of n-bit states for latch positions of the linear feedback shift register; obtaining the modulo remainder of the Nth state; and generating the Nth state directly from the modulo remainder and n-bit states.

Abstract: A secure credit card provides for secure transactions by users other than a holder of the secure credit card by providing storage for additional personal identification numbers (PINs) for authorized users. Transactions for authorized users may be controlled in accordance with individual user profiles stored in the secure credit card and which may be freely and flexibly established in regard to transaction amount, merchant restrictions and the like in response to recognition of a PIN corresponding to a holder of the secure credit card to whom the card is issued.

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.

Abstract: A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of operations for the circuit.

Abstract: A system and a method for measuring and quantitatively analyzing the jitter in repetitive electrical signals in a chip using a tester are described. The tester sorts chips based on the jitter measurements, thereby eliminating the need for external instrumentation. The waveform is sampled by the tester at various points of a period over a large number of periods and results are collected. The data is analyzed to determine the total range where the waveform is found to undergo a transition. The transition area is further analyzed to pinpoint the precise location of the transition for each period of the repetitive waveform. The data is used to quantify the jitter by means of statistical analyses, the results of which are used by the tester to sort the chips by comparing the calculated jitter characteristics to predetermined criteria.

Abstract: A system and method for testing first and second sets of electronic devices on a microchip is provided. The first set of devices receive input data and then send output data to a first multiple input shift register (MISR). The second set of devices receiving input data and then sending output data to a second MISR. The method includes determining a first seed signature value associated with the first MISR that induces the first MISR to have a first final signature value comprising a plurality of identical binary values when the first set of devices send valid output data to the first MISR when receiving a first predetermined sequence of input data.

Abstract: A computer random access memory is divided into first and second partitions. Each partition has its own operating system (OS). The first partition has a conventional OS and is designated for non-Internet use. The second partition is designated for secure Internet access, and has an OS specific for Internet usage. Software in the second partition cannot write or copy files in the second partition. The size of the second partition is fixed and unchangeable while said second partition is open. Each software application in the second partition is allocated a memory region that cannot be changed, thereby preventing memory overflow attacks. A secure memory is designated for temporary storage of software used in the second partition. Cyclic redundancy check (CRC) values are calculated for all files in the secure memory. To detect unauthorized file changes, CRC values are calculated for all files used in the second partition, and checked against values stored in the secure memory.

Abstract: A soft-fust test algorithm is distributed on-chip from an ABSIT engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad elements and repair those that are fixable. Using single-bit MISR error evaluation an ABSIT test sequence is executed concurrently on all arrays through the shift register chain. If any arrays are in error, redundancy compensation is employed and the ABIST test is repeated for all possible array redundant combinations until a functional configuration for each array is identified or all possible redundant combinations have been tried. Once functioning array configurations are verified, the associated soft-fuse states can be used to blow fuses and/or extracted for further system setup, permanent fuse-blowing and yield analysis. Multiple shift register chains driven by separate ABIST engines may be required to test all arrays on a chip.

Abstract: A system and a method for measuring and quantitatively analyzing the jitter in repetitive electrical signals in a chip using a tester are described. The tester sorts chips based on the jitter measurements, thereby eliminating the need for external instrumentation. The waveform is sampled by the tester at various points of a period over a large number of periods and results are collected. The data is analyzed to determine the total range where the waveform is found to undergo a transition. The transition area is further analyzed to pinpoint the precise location of the transition for each period of the repetitive waveform. The data is used to quantify the jitter by means of statistical analyses, the results of which are used by the tester to sort the chips by comparing the calculated jitter characteristics to predetermined criteria.