Patents by Inventor Francois Guyader
Francois Guyader has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260287799Abstract: The present description concerns a method for manufacturing a transparent optical structure 10, including a step of making a protective layer covering a conductive layer 21, by CVD deposition under vacuum, with thermally exposing to a first temperature T1 greater than, or equal to within 10%, to a second temperature T2 at least equal to 300°C for a first duration ?t1 greater than, or equal to within 10%, a second duration ?t2 at least equal to 60min; and then a subsequent step of thermally exposing to the temperature T2 for the duration ?t2.Type: ApplicationFiled: March 5, 2026Publication date: September 24, 2026Applicant: STMicroelectronics International N.V.Inventors: Maxime ARGOUD, Francois GUYADER, Pierre TISSIER
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Publication number: 20260287800Abstract: An optical diffuser includes a lower diffuser layer with a contact pad positioned thereon. The contact pad has a lateral edge with an inclination of less than or equal to 80°. At least one conductive via opening, at least partially filled with a conductive material, extends through the lower diffuser layer to reach a lower surface of the contact pad. A thin conductive track extends on the lower diffuser layer and over the lateral edge of the contact pad.Type: ApplicationFiled: March 11, 2026Publication date: September 24, 2026Applicant: STMicroelectronics International N.V.Inventor: Francois GUYADER
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Publication number: 20260047407Abstract: The present description concerns a method of manufacturing a first wafer, intended to be assembled to a second wafer by molecular bonding, including the successive steps of: forming a stack of layers at the surface of a substrate; and successive chemical etchings of the edges of said layers from the layer of the stack most distant from the substrate, across a smaller and smaller width.Type: ApplicationFiled: October 17, 2025Publication date: February 12, 2026Applicants: STMicroelectronics France, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Francois GUYADER, Pascal BESSON
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Patent number: 12328962Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.Type: GrantFiled: November 3, 2023Date of Patent: June 10, 2025Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research &Development) LimitedInventors: Francois Guyader, Sara Pellegrini, Bruce Rae
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Patent number: 12199131Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.Type: GrantFiled: June 30, 2022Date of Patent: January 14, 2025Assignee: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Frederic Lalanne, Yann Henrion, Francois Guyader, Pascal Fonteneau, Aurelien Seignard
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Patent number: 12057461Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.Type: GrantFiled: July 24, 2023Date of Patent: August 6, 2024Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Francois Guyader, Sara Pellegrini, Bruce Rae
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Publication number: 20240063235Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.Type: ApplicationFiled: November 3, 2023Publication date: February 22, 2024Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Francois GUYADER, Sara PELLEGRINI, Bruce RAE
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Patent number: 11901278Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.Type: GrantFiled: January 11, 2023Date of Patent: February 13, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Jean-Pierre Carrere, Francois Guyader
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Patent number: 11843008Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.Type: GrantFiled: October 11, 2021Date of Patent: December 12, 2023Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Francois Guyader, Sara Pellegrini, Bruce Rae
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Publication number: 20230369359Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Francois GUYADER, Sara PELLEGRINI, Bruce RAE
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Patent number: 11610933Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.Type: GrantFiled: May 21, 2021Date of Patent: March 21, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Frederic Lalanne, Laurent Gay, Pascal Fonteneau, Yann Henrion, Francois Guyader
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Patent number: 11581249Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.Type: GrantFiled: September 9, 2020Date of Patent: February 14, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Jean-Pierre Carrere, Francois Guyader
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Publication number: 20220344385Abstract: A semiconductor substrate includes a matrix of photosites. Each photosite is delimited by an isolation trench including polycrystalline silicon. A peripheral zone extends directly around the matrix of photosites. The peripheral zone includes dummy photosites delimited by isolation trenches including polycrystalline silicon. A density of polycrystalline silicon in the peripheral zone is between a density of polycrystalline silicon at an edge of the matrix of photosites and a density of polycrystalline silicon around the peripheral zone.Type: ApplicationFiled: April 20, 2022Publication date: October 27, 2022Applicant: STMicroelectronics (Crolles 2) SASInventor: Francois GUYADER
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Publication number: 20220336520Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Laurent GAY, Frederic LALANNE, Yann HENRION, Francois GUYADER, Pascal FONTENEAU, Aurelien SEIGNARD
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Patent number: 11398521Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.Type: GrantFiled: January 10, 2020Date of Patent: July 26, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Frederic Lalanne, Yann Henrion, Francois Guyader, Pascal Fonteneau, Aurelien Seignard
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Publication number: 20220115419Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.Type: ApplicationFiled: October 11, 2021Publication date: April 14, 2022Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Francois GUYADER, Sara PELLEGRINI, Bruce RAE
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Publication number: 20220037157Abstract: The present description concerns a method of manufacturing a first wafer, intended to be assembled to a second wafer by molecular bonding, including the successive steps of: forming a stack of layers at the surface of a substrate; and successive chemical etchings of the edges of said layers from the layer of the stack most distant from the substrate, across a smaller and smaller width.Type: ApplicationFiled: July 23, 2021Publication date: February 3, 2022Applicant: STMICROELECTRONICS SAInventors: Francois GUYADER, Pascal BESSON
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Publication number: 20210288102Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.Type: ApplicationFiled: May 21, 2021Publication date: September 16, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Frederic LALANNE, Laurent GAY, Pascal FONTENEAU, Yann HENRION, Francois GUYADER
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Patent number: 11031433Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.Type: GrantFiled: February 8, 2019Date of Patent: June 8, 2021Assignee: STMicroelectronics (Crolles) SASInventors: Frederic Lalanne, Laurent Gay, Pascal Fonteneau, Yann Henrion, Francois Guyader
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Publication number: 20210074618Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.Type: ApplicationFiled: September 9, 2020Publication date: March 11, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Jean-Pierre CARRERE, Francois GUYADER