Patents by Inventor Francois Guyader
Francois Guyader has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12328962Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.Type: GrantFiled: November 3, 2023Date of Patent: June 10, 2025Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research &Development) LimitedInventors: Francois Guyader, Sara Pellegrini, Bruce Rae
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Patent number: 12199131Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.Type: GrantFiled: June 30, 2022Date of Patent: January 14, 2025Assignee: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Frederic Lalanne, Yann Henrion, Francois Guyader, Pascal Fonteneau, Aurelien Seignard
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Patent number: 12057461Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.Type: GrantFiled: July 24, 2023Date of Patent: August 6, 2024Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Francois Guyader, Sara Pellegrini, Bruce Rae
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Patent number: 11901278Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.Type: GrantFiled: January 11, 2023Date of Patent: February 13, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Jean-Pierre Carrere, Francois Guyader
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Patent number: 11843008Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.Type: GrantFiled: October 11, 2021Date of Patent: December 12, 2023Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Francois Guyader, Sara Pellegrini, Bruce Rae
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Patent number: 11610933Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.Type: GrantFiled: May 21, 2021Date of Patent: March 21, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Frederic Lalanne, Laurent Gay, Pascal Fonteneau, Yann Henrion, Francois Guyader
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Patent number: 11581249Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.Type: GrantFiled: September 9, 2020Date of Patent: February 14, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Jean-Pierre Carrere, Francois Guyader
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Patent number: 11398521Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.Type: GrantFiled: January 10, 2020Date of Patent: July 26, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Frederic Lalanne, Yann Henrion, Francois Guyader, Pascal Fonteneau, Aurelien Seignard
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Patent number: 11031433Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.Type: GrantFiled: February 8, 2019Date of Patent: June 8, 2021Assignee: STMicroelectronics (Crolles) SASInventors: Frederic Lalanne, Laurent Gay, Pascal Fonteneau, Yann Henrion, Francois Guyader
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Patent number: 10446593Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.Type: GrantFiled: October 26, 2018Date of Patent: October 15, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Francois Guyader
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Patent number: 10362250Abstract: A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas. The image sensor includes, for each pixel, a protector extending at least partly into the substrate from the back of the substrate to ensure that the storage area is protected against back illumination.Type: GrantFiled: May 22, 2018Date of Patent: July 23, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Guyader, Francois Roy
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Publication number: 20190067342Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.Type: ApplicationFiled: October 26, 2018Publication date: February 28, 2019Applicant: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Francois Guyader
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Patent number: 10147748Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.Type: GrantFiled: May 22, 2017Date of Patent: December 4, 2018Assignee: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Francois Guyader
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Publication number: 20180270439Abstract: A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas. The image sensor includes, for each pixel, a protector extending at least partly into the substrate from the back of the substrate to ensure that the storage area is protected against back illumination.Type: ApplicationFiled: May 22, 2018Publication date: September 20, 2018Inventors: Francois Guyader, Francois Roy
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Patent number: 9998699Abstract: A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas. The image sensor includes, for each pixel, a protector extending at least partly into the substrate from the back of the substrate to ensure that the storage area is protected against back illumination.Type: GrantFiled: March 22, 2016Date of Patent: June 12, 2018Assignee: STMicroelectronics (Crolles 2) SASInventors: François Guyader, François Roy
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Publication number: 20180145100Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.Type: ApplicationFiled: May 22, 2017Publication date: May 24, 2018Applicant: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Francois Guyader
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Patent number: 9685475Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.Type: GrantFiled: September 8, 2015Date of Patent: June 20, 2017Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: Francois Guyader, Jean-Pierre Oddou, Stephane Allegret-Maret, Mickael Gros-Jean
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Patent number: 9648724Abstract: An electronic device has a rear plate that includes a substrate rear layer, a substrate front layer and a dielectric intermediate layer between the substrate rear and front layers. An electronic structure is on the substrate front layer and includes electronic components and electrical connections. The substrate rear layer includes a solid local region and a hollowed-out local region. The hollowed-out local region extends over all of the substrate rear layer. The substrate rear layer does not cover at least one local zone of the dielectric intermediate layer corresponding to the hollowed-out local region.Type: GrantFiled: December 2, 2015Date of Patent: May 9, 2017Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SAInventors: Nicolas Hotellier, François Guyader, Vincent Fiori, Richard Fournel, Frédéric Gianesello
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Publication number: 20170040285Abstract: A planar layer of a selected material is formed on a surface of a wafer exhibiting recesses. The formation process including the steps of: a) depositing a first layer of the selected material on the surface; b) performing a chemical mechanical polishing of the first layer; c) depositing a second layer of the selected material on the first layer; and d) performing a chemical mechanical polishing of the second layer.Type: ApplicationFiled: August 1, 2016Publication date: February 9, 2017Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Francois Guyader, Emmanuel Gourvest, Patrick Gros D'aillon
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Publication number: 20160099278Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.Type: ApplicationFiled: September 8, 2015Publication date: April 7, 2016Applicant: STMICROELECTRONICS (CROLLES 2) SASInventors: Francois Guyader, Jean-Pierre Oddou, Stephane Allegret-Maret, Mickael Gros-Jean