Patents by Inventor Francois Guyader

Francois Guyader has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260287799
    Abstract: The present description concerns a method for manufacturing a transparent optical structure 10, including a step of making a protective layer covering a conductive layer 21, by CVD deposition under vacuum, with thermally exposing to a first temperature T1 greater than, or equal to within 10%, to a second temperature T2 at least equal to 300°C for a first duration ?t1 greater than, or equal to within 10%, a second duration ?t2 at least equal to 60min; and then a subsequent step of thermally exposing to the temperature T2 for the duration ?t2.
    Type: Application
    Filed: March 5, 2026
    Publication date: September 24, 2026
    Applicant: STMicroelectronics International N.V.
    Inventors: Maxime ARGOUD, Francois GUYADER, Pierre TISSIER
  • Publication number: 20260287800
    Abstract: An optical diffuser includes a lower diffuser layer with a contact pad positioned thereon. The contact pad has a lateral edge with an inclination of less than or equal to 80°. At least one conductive via opening, at least partially filled with a conductive material, extends through the lower diffuser layer to reach a lower surface of the contact pad. A thin conductive track extends on the lower diffuser layer and over the lateral edge of the contact pad.
    Type: Application
    Filed: March 11, 2026
    Publication date: September 24, 2026
    Applicant: STMicroelectronics International N.V.
    Inventor: Francois GUYADER
  • Publication number: 20260047407
    Abstract: The present description concerns a method of manufacturing a first wafer, intended to be assembled to a second wafer by molecular bonding, including the successive steps of: forming a stack of layers at the surface of a substrate; and successive chemical etchings of the edges of said layers from the layer of the stack most distant from the substrate, across a smaller and smaller width.
    Type: Application
    Filed: October 17, 2025
    Publication date: February 12, 2026
    Applicants: STMicroelectronics France, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois GUYADER, Pascal BESSON
  • Patent number: 12328962
    Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: June 10, 2025
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research &Development) Limited
    Inventors: Francois Guyader, Sara Pellegrini, Bruce Rae
  • Patent number: 12199131
    Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: January 14, 2025
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent Gay, Frederic Lalanne, Yann Henrion, Francois Guyader, Pascal Fonteneau, Aurelien Seignard
  • Patent number: 12057461
    Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: August 6, 2024
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Francois Guyader, Sara Pellegrini, Bruce Rae
  • Publication number: 20240063235
    Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 22, 2024
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Francois GUYADER, Sara PELLEGRINI, Bruce RAE
  • Patent number: 11901278
    Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Pierre Carrere, Francois Guyader
  • Patent number: 11843008
    Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: December 12, 2023
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Francois Guyader, Sara Pellegrini, Bruce Rae
  • Publication number: 20230369359
    Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Francois GUYADER, Sara PELLEGRINI, Bruce RAE
  • Patent number: 11610933
    Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: March 21, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic Lalanne, Laurent Gay, Pascal Fonteneau, Yann Henrion, Francois Guyader
  • Patent number: 11581249
    Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: February 14, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Pierre Carrere, Francois Guyader
  • Publication number: 20220344385
    Abstract: A semiconductor substrate includes a matrix of photosites. Each photosite is delimited by an isolation trench including polycrystalline silicon. A peripheral zone extends directly around the matrix of photosites. The peripheral zone includes dummy photosites delimited by isolation trenches including polycrystalline silicon. A density of polycrystalline silicon in the peripheral zone is between a density of polycrystalline silicon at an edge of the matrix of photosites and a density of polycrystalline silicon around the peripheral zone.
    Type: Application
    Filed: April 20, 2022
    Publication date: October 27, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois GUYADER
  • Publication number: 20220336520
    Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent GAY, Frederic LALANNE, Yann HENRION, Francois GUYADER, Pascal FONTENEAU, Aurelien SEIGNARD
  • Patent number: 11398521
    Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: July 26, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent Gay, Frederic Lalanne, Yann Henrion, Francois Guyader, Pascal Fonteneau, Aurelien Seignard
  • Publication number: 20220115419
    Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.
    Type: Application
    Filed: October 11, 2021
    Publication date: April 14, 2022
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Francois GUYADER, Sara PELLEGRINI, Bruce RAE
  • Publication number: 20220037157
    Abstract: The present description concerns a method of manufacturing a first wafer, intended to be assembled to a second wafer by molecular bonding, including the successive steps of: forming a stack of layers at the surface of a substrate; and successive chemical etchings of the edges of said layers from the layer of the stack most distant from the substrate, across a smaller and smaller width.
    Type: Application
    Filed: July 23, 2021
    Publication date: February 3, 2022
    Applicant: STMICROELECTRONICS SA
    Inventors: Francois GUYADER, Pascal BESSON
  • Publication number: 20210288102
    Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 16, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic LALANNE, Laurent GAY, Pascal FONTENEAU, Yann HENRION, Francois GUYADER
  • Patent number: 11031433
    Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: June 8, 2021
    Assignee: STMicroelectronics (Crolles) SAS
    Inventors: Frederic Lalanne, Laurent Gay, Pascal Fonteneau, Yann Henrion, Francois Guyader
  • Publication number: 20210074618
    Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 11, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Pierre CARRERE, Francois GUYADER