Patents by Inventor Francois Guyader

Francois Guyader has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180270439
    Abstract: A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas. The image sensor includes, for each pixel, a protector extending at least partly into the substrate from the back of the substrate to ensure that the storage area is protected against back illumination.
    Type: Application
    Filed: May 22, 2018
    Publication date: September 20, 2018
    Inventors: Francois Guyader, Francois Roy
  • Patent number: 9998699
    Abstract: A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas. The image sensor includes, for each pixel, a protector extending at least partly into the substrate from the back of the substrate to ensure that the storage area is protected against back illumination.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: June 12, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: François Guyader, François Roy
  • Publication number: 20180145100
    Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.
    Type: Application
    Filed: May 22, 2017
    Publication date: May 24, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent Gay, Francois Guyader
  • Patent number: 9685475
    Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: June 20, 2017
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francois Guyader, Jean-Pierre Oddou, Stephane Allegret-Maret, Mickael Gros-Jean
  • Publication number: 20170134683
    Abstract: A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas. The image sensor includes, for each pixel, a protector extending at least partly into the substrate from the back of the substrate to ensure that the storage area is protected against back illumination.
    Type: Application
    Filed: March 22, 2016
    Publication date: May 11, 2017
    Inventors: François GUYADER, François ROY
  • Patent number: 9648724
    Abstract: An electronic device has a rear plate that includes a substrate rear layer, a substrate front layer and a dielectric intermediate layer between the substrate rear and front layers. An electronic structure is on the substrate front layer and includes electronic components and electrical connections. The substrate rear layer includes a solid local region and a hollowed-out local region. The hollowed-out local region extends over all of the substrate rear layer. The substrate rear layer does not cover at least one local zone of the dielectric intermediate layer corresponding to the hollowed-out local region.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: May 9, 2017
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA
    Inventors: Nicolas Hotellier, François Guyader, Vincent Fiori, Richard Fournel, Frédéric Gianesello
  • Publication number: 20170040285
    Abstract: A planar layer of a selected material is formed on a surface of a wafer exhibiting recesses. The formation process including the steps of: a) depositing a first layer of the selected material on the surface; b) performing a chemical mechanical polishing of the first layer; c) depositing a second layer of the selected material on the first layer; and d) performing a chemical mechanical polishing of the second layer.
    Type: Application
    Filed: August 1, 2016
    Publication date: February 9, 2017
    Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Francois Guyader, Emmanuel Gourvest, Patrick Gros D'aillon
  • Publication number: 20160366758
    Abstract: An electronic device has a rear plate that includes a substrate rear layer, a substrate front layer and a dielectric intermediate layer between the substrate rear and front layers. An electronic structure is on the substrate front layer and includes electronic components and electrical connections. The substrate rear layer includes a solid local region and a hollowed-out local region. The hollowed-out local region extends over all of the substrate rear layer. The substrate rear layer does not cover at least one local zone of the dielectric intermediate layer corresponding to the hollowed-out local region.
    Type: Application
    Filed: December 2, 2015
    Publication date: December 15, 2016
    Inventors: Nicolas HOTELLIER, François GUYADER, Vincent FIORI, Richard FOURNEL, Frédéric GIANESELLO
  • Publication number: 20160099278
    Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.
    Type: Application
    Filed: September 8, 2015
    Publication date: April 7, 2016
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francois Guyader, Jean-Pierre Oddou, Stephane Allegret-Maret, Mickael Gros-Jean
  • Patent number: 8716843
    Abstract: Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: May 6, 2014
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent Gay, Francois Guyader, Frederic Diette
  • Publication number: 20120273952
    Abstract: Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 1, 2012
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Laurent Gay, Francois Guyader, Frederic Diette
  • Patent number: 6887759
    Abstract: The invention concerns a method for forming, in a substrate (1) having a first type of conductivity, a MOS transistor, comprising the following steps: a) forming on the substrate an insulated gate (3); b) implanting a doping agent having a second type of conductivity; c) forming on the edges of the gate silicon nitride spacers; d) simultaneously oxidising the apparent surfaces of the substrate, the gate and the spacers; and e) drain and source implantation.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: May 3, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: François Guyader, Franck Arnaud
  • Publication number: 20040067612
    Abstract: The invention concerns a method for forming, in a substrate (1) having a first type of conductivity, a MOS transistor, comprising the following steps: a) forming on the substrate an insulated gate (3); b) implanting a doping agent having a second type of conductivity; c) forming on the edges of the gate silicon nitride spacers; d) simultaneously oxidising the apparent surfaces of the substrate, the gate and the spacers; and e) drain and source implantation.
    Type: Application
    Filed: January 23, 2003
    Publication date: April 8, 2004
    Inventors: Francois Guyader, Franck Arnaud