Patents by Inventor Francois Hebert

Francois Hebert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11144946
    Abstract: Certain exemplary embodiments described herein relate to digital downloading jukebox systems of the type that typically include a central server and remote jukebox devices that communicate with the central server for royalty accounting and/or content updates. More particularly, certain exemplary embodiments relate to jukebox systems that have revenue-enhancing features such as for example, music recommendation engines and bartender loyalty programs. Such innovative techniques help to both increase per jukebox revenue as well as keep jukebox patrons engaged with the jukebox.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: October 12, 2021
    Assignee: TouchTunes Music Corporation
    Inventors: Dominique Dion, Mounir Khenfir, Billy Panagiotopoulos, Christian Pompidor, Francois Beaumier, Frederic Baril, Sebastien Hebert
  • Publication number: 20210305143
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen CHEN, Hsin-Chang TSAI, Chun-Yi WU, Chia-Ching HUANG, Chih-Jen HSIAO, Wei-Chan CHANG, Francois HEBERT
  • Patent number: 11133246
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: September 28, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen Chen, Hsin-Chang Tsai, Chun-Yi Wu, Chia-Ching Huang, Chih-Jen Hsiao, Wei-Chan Chang, Francois Hebert
  • Patent number: 10896968
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: January 19, 2021
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K. Lui
  • Patent number: 10732022
    Abstract: A system and method for real-time management of liquid bottles contents in a restauration establishment includes a controller and at least one bottle support base coupled to the controller. Each bottle support base includes a bottle-receiving surface, a first sensor that produces a first signal indicative of a weight of a bottle deposited on the surface; a second sensor for reading an identification element on the bottle and for producing a second signal indicative thereof; and a transmitter for transmitting to the controller data indicative of the first and second signal. The controller implements numerous functionalities that are derived from its assessment of the volumes of alcohol in the bottles using the data received from the support bases.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: August 4, 2020
    Assignee: Apéros Systèmes Inc.
    Inventors: Gilles Clément, François Hébert, Mathieu Beaupré, Michel Corriveau
  • Patent number: 10700265
    Abstract: A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing area comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: June 30, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Francois Hebert, Seong Woo Lee, Jong Yeul Jeong, Hee Baeg An, Kang Sup Shin, Seong Min Choe, Young Joon Kim
  • Patent number: 10686037
    Abstract: A semiconductor structure includes an insulating substrate, an engineered layer, a semiconductor layer, and an isolation structure. The engineered layer is surrounding the insulating substrate. The semiconductor layer, which includes a first region and a second region,. is formed over the engineered layer. The isolation structure is formed in the semiconductor layer and located between the first region and the second region. A first transistor and a second transistor are formed in the first region and the second region respectively.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: June 16, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Francois Hebert
  • Patent number: 10586863
    Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: March 10, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Francois Hebert, Yon Sup Pang, Yu Shin Ryu, Seong Min Cho, Ju Ho Kim
  • Patent number: 10580769
    Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 3, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Francois Hebert
  • Publication number: 20200027951
    Abstract: A semiconductor structure includes an insulating substrate, an engineered layer, a semiconductor layer, a gate structure, a source region, and a drain region. The engineered layer is surrounding the insulating substrate. The semiconductor layer including a first region and a second region is formed over the engineered layer. The gate structure is formed over the semiconductor layer. The source region and the drain region are formed in the semiconductor layer and located on both sides of the first gate structure.
    Type: Application
    Filed: July 19, 2018
    Publication date: January 23, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventor: Francois HEBERT
  • Patent number: 10468526
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: November 5, 2019
    Assignee: Alpha and Omega Semiconductor, Inc.
    Inventors: François Hébert, Madhur Bobde, Anup Bhalla
  • Patent number: 10446677
    Abstract: A semiconductor structure is provided. The semiconductor structure includes an insulating substrate including a first region and a second region; an engineered layer surrounding the insulating substrate; a nucleation layer formed on the engineered layer; a buffer layer formed on the nucleation layer; a first epitaxial layer formed on the buffer layer; a second epitaxial layer formed on the first epitaxial layer; an isolation structure at least formed in the second epitaxial layer, the first epitaxial layer and the nucleation layer, and located between the first region and the second region; a first gate, a first source and a first drain formed on the second epitaxial layer within the first region; and a second gate, a second source, and a second drain formed on the second epitaxial layer within the second region.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: October 15, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Francois Hebert
  • Publication number: 20190288099
    Abstract: A semiconductor structure is provided. The semiconductor structure includes an insulating substrate including a first region and a second region; an engineered layer surrounding the insulating substrate; a nucleation layer formed on the engineered layer; a buffer layer formed on the nucleation layer; a first epitaxial layer formed on the buffer layer; a second epitaxial layer formed on the first epitaxial layer; an isolation structure at least formed in the second epitaxial layer, the first epitaxial layer and the nucleation layer, and located between the first region and the second region; a first gate, a first source and a first drain formed on the second epitaxial layer within the first region; and a second gate, a second source, and a second drain formed on the second epitaxial layer within the second region.
    Type: Application
    Filed: March 16, 2018
    Publication date: September 19, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventor: Francois HEBERT
  • Publication number: 20190267365
    Abstract: Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Francois HEBERT, Steven R. RIVET, Michael ALTHAR, Peter OAKLANDER
  • Publication number: 20190148363
    Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.
    Type: Application
    Filed: January 11, 2019
    Publication date: May 16, 2019
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Francois HEBERT
  • Patent number: 10290618
    Abstract: Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: May 14, 2019
    Assignee: INTERSIL AMERICAS LLC
    Inventors: Francois Hebert, Steven R. Rivet, Michael Althar, Peter Oaklander
  • Publication number: 20190072424
    Abstract: A system and method for real-time management of liquid bottles contents in a restauration establishment includes a controller and at least one bottle support base coupled to the controller. Each bottle support base includes a bottle-receiving surface, a first sensor that produces a first signal indicative of a weight of a bottle deposited on the surface; a second sensor for reading an identification element on the bottle and for producing a second signal indicative thereof; and a transmitter for transmitting to the controller data indicative of the first and second signal. The controller implements numerous functionalities that are derived from its assessment of the volumes of alcohol in the bottles using the data received from the support bases.
    Type: Application
    Filed: March 14, 2017
    Publication date: March 7, 2019
    Inventors: Gilles Clément, François Hébert, Mathieu Beaupré, Michel Corriveau
  • Patent number: 10224321
    Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: March 5, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Francois Hebert
  • Patent number: 10224411
    Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Shekar Mallikarjunaswamy, Francois Hebert
  • Patent number: 10170397
    Abstract: A semiconductor device includes a via structure penetrating through a substrate, a top metal layer and an electronic component over the via structure, and a bottom metal layer and another electronic component below the via structure. The via structure includes a through hole penetrating from a first surface to an opposite second surface of a substrate, a filling insulating layer within the through hole, a first conductive layer, which is within the through hole and surrounds the filling insulating layer, wherein a portion of the first conductive layer is below the filling insulating layer and at the bottom of the through hole. The via structure further includes a first insulating layer, which is on the sidewalls of the through hole and surrounds the first conductive layer.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 1, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Li-Che Chen, Francois Hebert