Patents by Inventor Francois Hebert

Francois Hebert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10468526
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: November 5, 2019
    Assignee: Alpha and Omega Semiconductor, Inc.
    Inventors: François Hébert, Madhur Bobde, Anup Bhalla
  • Patent number: 10446677
    Abstract: A semiconductor structure is provided. The semiconductor structure includes an insulating substrate including a first region and a second region; an engineered layer surrounding the insulating substrate; a nucleation layer formed on the engineered layer; a buffer layer formed on the nucleation layer; a first epitaxial layer formed on the buffer layer; a second epitaxial layer formed on the first epitaxial layer; an isolation structure at least formed in the second epitaxial layer, the first epitaxial layer and the nucleation layer, and located between the first region and the second region; a first gate, a first source and a first drain formed on the second epitaxial layer within the first region; and a second gate, a second source, and a second drain formed on the second epitaxial layer within the second region.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: October 15, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Francois Hebert
  • Publication number: 20190288099
    Abstract: A semiconductor structure is provided. The semiconductor structure includes an insulating substrate including a first region and a second region; an engineered layer surrounding the insulating substrate; a nucleation layer formed on the engineered layer; a buffer layer formed on the nucleation layer; a first epitaxial layer formed on the buffer layer; a second epitaxial layer formed on the first epitaxial layer; an isolation structure at least formed in the second epitaxial layer, the first epitaxial layer and the nucleation layer, and located between the first region and the second region; a first gate, a first source and a first drain formed on the second epitaxial layer within the first region; and a second gate, a second source, and a second drain formed on the second epitaxial layer within the second region.
    Type: Application
    Filed: March 16, 2018
    Publication date: September 19, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventor: Francois HEBERT
  • Publication number: 20190267365
    Abstract: Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Francois HEBERT, Steven R. RIVET, Michael ALTHAR, Peter OAKLANDER
  • Publication number: 20190148363
    Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.
    Type: Application
    Filed: January 11, 2019
    Publication date: May 16, 2019
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Francois HEBERT
  • Patent number: 10290618
    Abstract: Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: May 14, 2019
    Assignee: INTERSIL AMERICAS LLC
    Inventors: Francois Hebert, Steven R. Rivet, Michael Althar, Peter Oaklander
  • Publication number: 20190072424
    Abstract: A system and method for real-time management of liquid bottles contents in a restauration establishment includes a controller and at least one bottle support base coupled to the controller. Each bottle support base includes a bottle-receiving surface, a first sensor that produces a first signal indicative of a weight of a bottle deposited on the surface; a second sensor for reading an identification element on the bottle and for producing a second signal indicative thereof; and a transmitter for transmitting to the controller data indicative of the first and second signal. The controller implements numerous functionalities that are derived from its assessment of the volumes of alcohol in the bottles using the data received from the support bases.
    Type: Application
    Filed: March 14, 2017
    Publication date: March 7, 2019
    Inventors: Gilles Clément, François Hébert, Mathieu Beaupré, Michel Corriveau
  • Patent number: 10224321
    Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: March 5, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Francois Hebert
  • Patent number: 10224411
    Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Shekar Mallikarjunaswamy, Francois Hebert
  • Patent number: 10170397
    Abstract: A semiconductor device includes a via structure penetrating through a substrate, a top metal layer and an electronic component over the via structure, and a bottom metal layer and another electronic component below the via structure. The via structure includes a through hole penetrating from a first surface to an opposite second surface of a substrate, a filling insulating layer within the through hole, a first conductive layer, which is within the through hole and surrounds the filling insulating layer, wherein a portion of the first conductive layer is below the filling insulating layer and at the bottom of the through hole. The via structure further includes a first insulating layer, which is on the sidewalls of the through hole and surrounds the first conductive layer.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 1, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Li-Che Chen, Francois Hebert
  • Publication number: 20180240965
    Abstract: A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing area comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.
    Type: Application
    Filed: April 19, 2018
    Publication date: August 23, 2018
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Francois HEBERT, Seong Woo LEE, Jong Yeul JEONG, Hee Baeg AN, Kang Sup SHIN, Seong Min CHOE, Young Joon KIM
  • Patent number: 10003013
    Abstract: A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing are comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: June 19, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Francois Hebert, Seong Woo Lee, Jong Yeul Jeong, Hee Baeg An, Kang Sup Shin, Seong Min Choe, Young Joon Kim
  • Patent number: 9991192
    Abstract: Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: June 5, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Francois Hebert
  • Publication number: 20180102435
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.
    Type: Application
    Filed: December 8, 2017
    Publication date: April 12, 2018
    Inventors: François Hébert, Madjur Bobde, Anup Bhalla
  • Patent number: 9893099
    Abstract: The present disclosure relates to a photo sensor module. The thickness and size of an IC chip may be reduced by manufacturing a photo sensor based on a semiconductor substrate and improving the structure to place a UV sensor on the upper section of an active device or a passive device. The photo sensor module includes a semiconductor substrate, a field oxide layer, formed on the semiconductor substrate, and a photo sensor comprising a photo diode formed on the field oxide layer.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: February 13, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Francois Hebert, Seong Min Choe
  • Patent number: 9882049
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: January 30, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: François Hébert, Madhur Bobde, Anup Bhalla
  • Patent number: 9876012
    Abstract: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: January 23, 2018
    Assignee: INTERSIL AMERICAS LLC
    Inventor: Francois Hebert
  • Patent number: 9876072
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: January 23, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: François Hébert
  • Publication number: 20180012823
    Abstract: A semiconductor device includes a via structure penetrating through a substrate, a top metal layer and an electronic component over the via structure, and a bottom metal layer and another electronic component below the via structure. The via structure includes a through hole penetrating from a first surface to an opposite second surface of a substrate, a filling insulating layer within the through hole, a first conductive layer, which is within the through hole and surrounds the filling insulating layer, wherein a portion of the first conductive layer is below the filling insulating layer and at the bottom of the through hole. The via structure further includes a first insulating layer, which is on the sidewalls of the through hole and surrounds the first conductive layer.
    Type: Application
    Filed: July 7, 2016
    Publication date: January 11, 2018
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Li-Che CHEN, Francois HEBERT
  • Patent number: 9864020
    Abstract: A vertical Hall sensor, a Hall sensor module, and a method for manufacturing the same are provided. By applying a trench structure inside a substrate with respect to a ground terminal, a directional component parallel to surface of the substrate is maximized with respect to a current flow to detect the magnetic field with improved sensitivity.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: January 9, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Francois Hebert